307 lines
8.3 KiB
ArmAsm
307 lines
8.3 KiB
ArmAsm
/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CPU_MACROS_S
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#define CPU_MACROS_S
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#include <arch.h>
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#include <assert_macros.S>
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#include <lib/cpus/errata_report.h>
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#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
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(MIDR_PN_MASK << MIDR_PN_SHIFT)
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/* The number of CPU operations allowed */
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#define CPU_MAX_PWR_DWN_OPS 2
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/* Special constant to specify that CPU has no reset function */
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#define CPU_NO_RESET_FUNC 0
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#define CPU_NO_EXTRA1_FUNC 0
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#define CPU_NO_EXTRA2_FUNC 0
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/* Word size for 64-bit CPUs */
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#define CPU_WORD_SIZE 8
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/*
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* Whether errata status needs reporting. Errata status is printed in debug
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* builds for both BL1 and BL31 images.
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*/
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#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG
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# define REPORT_ERRATA 1
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#else
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# define REPORT_ERRATA 0
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#endif
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.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
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.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE
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.equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE
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.equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE
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#ifndef IMAGE_AT_EL3
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.equ CPU_RESET_FUNC_SIZE, 0
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#endif
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/* The power down core and cluster is needed only in BL31 */
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#ifndef IMAGE_BL31
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.equ CPU_PWR_DWN_OPS_SIZE, 0
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#endif
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/* Fields required to print errata status. */
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#if !REPORT_ERRATA
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.equ CPU_ERRATA_FUNC_SIZE, 0
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#endif
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/* Only BL31 requieres mutual exclusion and printed flag. */
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#if !(REPORT_ERRATA && defined(IMAGE_BL31))
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.equ CPU_ERRATA_LOCK_SIZE, 0
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.equ CPU_ERRATA_PRINTED_SIZE, 0
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#endif
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#if !defined(IMAGE_BL31) || !CRASH_REPORTING
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.equ CPU_REG_DUMP_SIZE, 0
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#endif
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/*
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* Define the offsets to the fields in cpu_ops structure.
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* Every offset is defined based in the offset and size of the previous
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* field.
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*/
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.equ CPU_MIDR, 0
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.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
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.equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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.equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
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.equ CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
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.equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
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.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
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.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
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.equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE
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.equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE
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/*
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* Write given expressions as quad words
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*
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* _count:
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* Write at least _count quad words. If the given number of
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* expressions is less than _count, repeat the last expression to
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* fill _count quad words in total
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* _rest:
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* Optional list of expressions. _this is for parameter extraction
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* only, and has no significance to the caller
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*
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* Invoked as:
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* fill_constants 2, foo, bar, blah, ...
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*/
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.macro fill_constants _count:req, _this, _rest:vararg
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.ifgt \_count
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/* Write the current expression */
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.ifb \_this
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.error "Nothing to fill"
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.endif
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.quad \_this
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/* Invoke recursively for remaining expressions */
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.ifnb \_rest
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fill_constants \_count-1, \_rest
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.else
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fill_constants \_count-1, \_this
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.endif
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.endif
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.endm
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/*
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* Declare CPU operations
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*
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* _name:
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* Name of the CPU for which operations are being specified
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* _midr:
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* Numeric value expected to read from CPU's MIDR
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* _resetfunc:
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* Reset function for the CPU. If there's no CPU reset function,
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* specify CPU_NO_RESET_FUNC
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* _extra1:
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* This is a placeholder for future per CPU operations. Currently,
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* some CPUs use this entry to set a test function to determine if
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* the workaround for CVE-2017-5715 needs to be applied or not.
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* _extra2:
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* This is a placeholder for future per CPU operations. Currently
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* some CPUs use this entry to set a function to disable the
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* workaround for CVE-2018-3639.
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* _e_handler:
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* This is a placeholder for future per CPU exception handlers.
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* CPU_MAX_PWR_DWN_OPS number of functions may be specified.
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* Starting at power level 0, these functions shall handle power
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* down at subsequent power levels. If there aren't exactly
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* CPU_MAX_PWR_DWN_OPS functions, the last specified one will be
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* used to handle power down at subsequent levels
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*/
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.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
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_extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg
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.section cpu_ops, "a"
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.align 3
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.type cpu_ops_\_name, %object
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.quad \_midr
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#if defined(IMAGE_AT_EL3)
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.quad \_resetfunc
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#endif
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.quad \_extra1
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.quad \_extra2
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.quad \_e_handler
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#ifdef IMAGE_BL31
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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#endif
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#if REPORT_ERRATA
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.ifndef \_name\()_cpu_str
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/*
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* Place errata reported flag, and the spinlock to arbitrate access to
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* it in the data section.
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*/
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.pushsection .data
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define_asm_spinlock \_name\()_errata_lock
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\_name\()_errata_reported:
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.word 0
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.popsection
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/* Place CPU string in rodata */
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.pushsection .rodata
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\_name\()_cpu_str:
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.asciz "\_name"
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.popsection
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.endif
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/*
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* Mandatory errata status printing function for CPUs of
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* this class.
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*/
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.quad \_name\()_errata_report
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#ifdef IMAGE_BL31
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/* Pointers to errata lock and reported flag */
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.quad \_name\()_errata_lock
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.quad \_name\()_errata_reported
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#endif
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#endif
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#if defined(IMAGE_BL31) && CRASH_REPORTING
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.quad \_name\()_cpu_reg_dump
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#endif
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.endm
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \
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\_power_down_ops
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.endm
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.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
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_e_handler:req, _power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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0, 0, \_e_handler, \_power_down_ops
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.endm
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.macro declare_cpu_ops_wa _name:req, _midr:req, \
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_resetfunc:req, _extra1:req, _extra2:req, \
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_power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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\_extra1, \_extra2, 0, \_power_down_ops
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.endm
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#if REPORT_ERRATA
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/*
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* Print status of a CPU errata
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*
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* _chosen:
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* Identifier indicating whether or not a CPU errata has been
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* compiled in.
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* _cpu:
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* Name of the CPU
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* _id:
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* Errata identifier
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* _rev_var:
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* Register containing the combined value CPU revision and variant
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* - typically the return value of cpu_get_rev_var
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*/
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.macro report_errata _chosen, _cpu, _id, _rev_var=x8
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/* Stash a string with errata ID */
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.pushsection .rodata
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\_cpu\()_errata_\_id\()_str:
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.asciz "\_id"
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.popsection
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/* Check whether errata applies */
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mov x0, \_rev_var
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/* Shall clobber: x0-x7 */
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bl check_errata_\_id
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.ifeq \_chosen
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/*
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* Errata workaround has not been compiled in. If the errata would have
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* applied had it been compiled in, print its status as missing.
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*/
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cbz x0, 900f
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mov x0, #ERRATA_MISSING
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.endif
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900:
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adr x1, \_cpu\()_cpu_str
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adr x2, \_cpu\()_errata_\_id\()_str
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bl errata_print_msg
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.endm
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#endif
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/*
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* This macro is used on some CPUs to detect if they are vulnerable
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* to CVE-2017-5715.
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*/
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.macro cpu_check_csv2 _reg _label
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mrs \_reg, id_aa64pfr0_el1
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ubfx \_reg, \_reg, #ID_AA64PFR0_CSV2_SHIFT, #ID_AA64PFR0_CSV2_LENGTH
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/*
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* If the field equals 1, branch targets trained in one context cannot
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* affect speculative execution in a different context.
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*
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* If the field equals 2, it means that the system is also aware of
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* SCXTNUM_ELx register contexts. We aren't using them in the TF, so we
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* expect users of the registers to do the right thing.
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*
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* Only apply mitigations if the value of this field is 0.
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*/
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#if ENABLE_ASSERTIONS
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cmp \_reg, #3 /* Only values 0 to 2 are expected */
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ASM_ASSERT(lo)
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#endif
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cmp \_reg, #0
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bne \_label
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.endm
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/*
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* Helper macro that reads the part number of the current
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* CPU and jumps to the given label if it matches the CPU
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* MIDR provided.
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*
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* Clobbers x0.
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*/
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.macro jump_if_cpu_midr _cpu_midr, _label
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mrs x0, midr_el1
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ubfx x0, x0, MIDR_PN_SHIFT, #12
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cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.eq \_label
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.endm
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#endif /* CPU_MACROS_S */
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