203 lines
5.7 KiB
Plaintext
203 lines
5.7 KiB
Plaintext
/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "rk312x.dtsi"
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/ {
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compatible = "rockchip,rk3128";
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rng: rng@100fc000 {
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compatible = "rockchip,cryptov1-rng";
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reg = <0x100fc000 0x4000>;
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clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
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clock-names = "clk_crypto", "hclk_crypto";
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assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
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assigned-clock-rates = <150000000>, <100000000>;
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resets = <&cru SRST_CRYPTO>;
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reset-names = "reset";
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status = "disabled";
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};
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qos_ebc: qos@1012f080 {
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compatible = "syscon";
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reg = <0x1012f080 0x20>;
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};
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hdmi: hdmi@20034000 {
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compatible = "rockchip,rk3128-inno-hdmi";
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reg = <0x20034000 0x4000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VIO0>, <&cru PCLK_HDMI>;
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clock-names = "aclk", "pclk";
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rockchip,grf = <&grf>;
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pinctrl-names = "default";
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pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>;
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#address-cells = <1>;
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#size-cells = <0>;
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#sound-dai-cells = <0>;
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status = "disabled";
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hdmi_in: port {
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#address-cells = <1>;
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#size-cells = <0>;
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hdmi_in_vop: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vop_out_hdmi>;
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};
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};
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};
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};
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&codec {
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/*
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* Override the i2s_clk since codec connects to i2s_8ch in rk3128,
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* which is different from rk3126.
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*/
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clock-names = "g_pclk_acodec", "i2s_clk";
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clocks = <&cru PCLK_ACODEC>, <&cru SCLK_I2S0>;
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};
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&cpu0_opp_table {
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rockchip,leakage-scaling-sel = <
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1 254 0
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>;
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rockchip,leakage-voltage-sel = <
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1 14 0
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15 35 1
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36 254 2
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>;
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <950000 950000 1425000>;
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opp-microvolt-L0 = <950000 950000 1425000>;
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opp-microvolt-L1 = <950000 950000 1425000>;
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opp-microvolt-L2 = <950000 950000 1425000>;
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clock-latency-ns = <40000>;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000 950000 1425000>;
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opp-microvolt-L0 = <950000 950000 1425000>;
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opp-microvolt-L1 = <950000 950000 1425000>;
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opp-microvolt-L2 = <950000 950000 1425000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt-L0 = <950000 950000 1425000>;
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opp-microvolt-L1 = <950000 950000 1425000>;
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opp-microvolt-L2 = <950000 950000 1425000>;
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clock-latency-ns = <40000>;
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};
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opp-696000000 {
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opp-hz = /bits/ 64 <696000000>;
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opp-microvolt = <1150000 1150000 1425000>;
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opp-microvolt-L0 = <975000 975000 1425000>;
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opp-microvolt-L1 = <975000 975000 1425000>;
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opp-microvolt-L2 = <975000 975000 1425000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1075000 1075000 1425000>;
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opp-microvolt-L0 = <1075000 1075000 1425000>;
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opp-microvolt-L1 = <1050000 1050000 1425000>;
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opp-microvolt-L2 = <1000000 1000000 1425000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1200000 1200000 1425000>;
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opp-microvolt-L0 = <1200000 1200000 1425000>;
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opp-microvolt-L1 = <1175000 1175000 1425000>;
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opp-microvolt-L2 = <1125000 1125000 1425000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1325000 1325000 1425000>;
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opp-microvolt-L0 = <1325000 1325000 1425000>;
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opp-microvolt-L1 = <1300000 1300000 1425000>;
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opp-microvolt-L2 = <1250000 1250000 1425000>;
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clock-latency-ns = <40000>;
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};
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};
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&pd_vio {
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pm_qos = <&qos_rga>,
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<&qos_ebc>,
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<&qos_iep>,
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<&qos_lcdc0>,
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<&qos_vip0>;
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};
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&sdmmc_pwren {
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rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
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};
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&video_phy {
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status = "okay";
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};
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&vop_mmu {
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rockchip,skip-mmu-read;
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};
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&vop_out {
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#address-cells = <1>;
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#size-cells = <0>;
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vop_out_dsi: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dsi_in_vop>;
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};
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vop_out_lvds: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&lvds_in_vop>;
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};
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vop_out_hdmi: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&hdmi_in_vop>;
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};
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};
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