android13/kernel-5.10/arch/arm/boot/dts/rv1106-uvc.dtsi

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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*/
/ {
};
&cru {
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
<&cru ARMCLK>,
<&cru CLK_50M_SRC>, <&cru CLK_100M_SRC>,
<&cru CLK_150M_SRC>, <&cru CLK_200M_SRC>,
<&cru CLK_250M_SRC>, <&cru CLK_300M_SRC>,
<&cru CLK_339M_SRC>, <&cru CLK_400M_SRC>,
<&cru CLK_450M_SRC>, <&cru CLK_500M_SRC>,
<&cru ACLK_PERI_ROOT>, <&cru HCLK_PERI_ROOT>,
<&cru PCLK_PERI_ROOT>, <&cru ACLK_BUS_ROOT>,
<&cru PCLK_TOP_ROOT>, <&cru PCLK_PMU_ROOT>,
<&cru HCLK_PMU_ROOT>;
assigned-clock-rates =
<983040000>, <1188000000>,
<1104000000>,
<50000000>, <100000000>,
<150000000>, <200000000>,
<250000000>, <300000000>,
<340000000>, <400000000>,
<450000000>, <500000000>,
<400000000>, <200000000>,
<100000000>, <300000000>,
<100000000>, <100000000>,
<200000000>;
};
&fiq_debugger {
rockchip,irq-mode-enable = <1>;
status = "okay";
};
&i2s0_8ch {
status = "okay";
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0>,
<&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>,
<&cru PLL_GPLL>, <&cru PLL_GPLL>;
clock-names = "mclk_tx", "mclk_rx", "hclk",
"mclk_tx_src", "mclk_rx_src",
"mclk_root0", "mclk_root1";
rockchip,mclk-calibrate;
};
&mpp_srv {
status = "okay";
};
&mpp_vcodec {
status = "okay";
};
&npu {
status = "okay";
};
&rga2 {
status = "okay";
};
&rkvenc {
status = "okay";
};
&rkvenc_pp {
status = "okay";
};
&rng {
status = "okay";
};
&rve {
status = "okay";
};
&u2phy {
status = "okay";
};
&u2phy_otg {
status = "okay";
};
&usbdrd {
status = "okay";
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
status = "okay";
};