473 lines
11 KiB
C
473 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#include "rk628.h"
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#include "rk628_cru.h"
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#define REFCLK_RATE 24000000UL
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#define MIN_FREF_RATE 10000000UL
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#define MAX_FREF_RATE 800000000UL
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#define MIN_FREFDIV_RATE 1000000UL
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#define MAX_FREFDIV_RATE 100000000UL
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#define MIN_FVCO_RATE 600000000UL
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#define MAX_FVCO_RATE 1600000000UL
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#define MIN_FOUTPOSTDIV_RATE 12000000UL
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#define MAX_FOUTPOSTDIV_RATE 1600000000UL
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static void rational_best_approximation(unsigned long given_numerator,
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unsigned long given_denominator,
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unsigned long max_numerator,
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unsigned long max_denominator,
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unsigned long *best_numerator,
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unsigned long *best_denominator)
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{
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unsigned long n, d, n0, d0, n1, d1;
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n = given_numerator;
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d = given_denominator;
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n0 = d1 = 0;
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n1 = d0 = 1;
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for (;;) {
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unsigned long t, a;
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if ((n1 > max_numerator) || (d1 > max_denominator)) {
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n1 = n0;
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d1 = d0;
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break;
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}
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if (d == 0)
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break;
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t = d;
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a = n / d;
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d = n % d;
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n = t;
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t = n0 + a * n1;
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n0 = n1;
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n1 = t;
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t = d0 + a * d1;
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d0 = d1;
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d1 = t;
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}
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*best_numerator = n1;
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*best_denominator = d1;
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}
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static unsigned long rk628_cru_clk_get_rate_pll(struct rk628 *rk628,
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unsigned int id)
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{
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unsigned long parent_rate = REFCLK_RATE;
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u32 postdiv1, fbdiv, dsmpd, postdiv2, refdiv, frac, bypass;
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u32 con0, con1, con2;
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u64 foutvco, foutpostdiv;
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u32 offset, val;
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rk628_i2c_read(rk628, CRU_MODE_CON00, &val);
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if (id == CGU_CLK_CPLL) {
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val &= CLK_CPLL_MODE_MASK;
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val >>= CLK_CPLL_MODE_SHIFT;
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if (val == CLK_CPLL_MODE_OSC)
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return parent_rate;
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offset = 0x00;
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} else {
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val &= CLK_GPLL_MODE_MASK;
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val >>= CLK_GPLL_MODE_SHIFT;
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if (val == CLK_GPLL_MODE_OSC)
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return parent_rate;
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offset = 0x20;
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}
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rk628_i2c_read(rk628, offset + CRU_CPLL_CON0, &con0);
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rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1);
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rk628_i2c_read(rk628, offset + CRU_CPLL_CON2, &con2);
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bypass = (con0 & PLL_BYPASS_MASK) >> PLL_BYPASS_SHIFT;
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postdiv1 = (con0 & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
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fbdiv = (con0 & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
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dsmpd = (con1 & PLL_DSMPD_MASK) >> PLL_DSMPD_SHIFT;
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postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
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refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
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frac = (con2 & PLL_FRAC_MASK) >> PLL_FRAC_SHIFT;
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if (bypass)
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return parent_rate;
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foutvco = parent_rate * fbdiv;
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do_div(foutvco, refdiv);
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if (!dsmpd) {
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u64 frac_rate = (u64)parent_rate * frac;
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do_div(frac_rate, refdiv);
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foutvco += frac_rate >> 24;
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}
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foutpostdiv = foutvco;
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do_div(foutpostdiv, postdiv1);
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do_div(foutpostdiv, postdiv2);
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return foutpostdiv;
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}
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static unsigned long rk628_cru_clk_set_rate_pll(struct rk628 *rk628,
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unsigned int id,
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unsigned long rate)
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{
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unsigned long fin = REFCLK_RATE, fout = rate;
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u8 min_refdiv, max_refdiv, postdiv;
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u8 dsmpd = 1, postdiv1 = 0, postdiv2 = 0, refdiv = 0;
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u16 fbdiv = 0;
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u32 frac = 0;
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u64 foutvco, foutpostdiv;
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u32 offset, val;
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/*
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* FREF : 10MHz ~ 800MHz
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* FREFDIV : 1MHz ~ 40MHz
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* FOUTVCO : 400MHz ~ 1.6GHz
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* FOUTPOSTDIV : 8MHz ~ 1.6GHz
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*/
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if (fin < MIN_FREF_RATE || fin > MAX_FREF_RATE)
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return 0;
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if (fout < MIN_FOUTPOSTDIV_RATE || fout > MAX_FOUTPOSTDIV_RATE)
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return 0;
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if (id == CGU_CLK_CPLL)
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offset = 0x00;
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else
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offset = 0x20;
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(1));
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if (fin == fout) {
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON0, PLL_BYPASS(1));
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0));
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while (1) {
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rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &val);
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if (val & PLL_LOCK)
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break;
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}
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return fin;
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}
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min_refdiv = fin / MAX_FREFDIV_RATE + 1;
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max_refdiv = fin / MIN_FREFDIV_RATE;
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if (max_refdiv > 64)
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max_refdiv = 64;
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if (fout < MIN_FVCO_RATE) {
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postdiv = MIN_FVCO_RATE / fout + 1;
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for (postdiv2 = 1; postdiv2 < 8; postdiv2++) {
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if (postdiv % postdiv2)
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continue;
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postdiv1 = postdiv / postdiv2;
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if (postdiv1 > 0 && postdiv1 < 8)
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break;
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}
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if (postdiv2 > 7)
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return 0;
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fout *= postdiv1 * postdiv2;
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} else {
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postdiv1 = 1;
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postdiv2 = 1;
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}
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for (refdiv = min_refdiv; refdiv <= max_refdiv; refdiv++) {
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u64 tmp, frac_rate;
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if (fin % refdiv)
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continue;
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tmp = (u64)fout * refdiv;
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do_div(tmp, fin);
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fbdiv = tmp;
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if (fbdiv < 10 || fbdiv > 1600)
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continue;
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tmp = (u64)fbdiv * fin;
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do_div(tmp, refdiv);
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if (fout < MIN_FVCO_RATE || fout > MAX_FVCO_RATE)
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continue;
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frac_rate = fout - tmp;
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if (frac_rate) {
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tmp = (u64)frac_rate * refdiv;
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tmp <<= 24;
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do_div(tmp, fin);
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frac = tmp;
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dsmpd = 0;
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}
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break;
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}
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/*
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* If DSMPD = 1 (DSM is disabled, "integer mode")
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* FOUTVCO = FREF / REFDIV * FBDIV
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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*
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* If DSMPD = 0 (DSM is enabled, "fractional mode")
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* FOUTVCO = FREF / REFDIV * (FBDIV + FRAC / 2^24)
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* FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
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*/
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foutvco = fin * fbdiv;
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do_div(foutvco, refdiv);
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if (!dsmpd) {
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u64 frac_rate = (u64)fin * frac;
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do_div(frac_rate, refdiv);
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foutvco += frac_rate >> 24;
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}
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foutpostdiv = foutvco;
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do_div(foutpostdiv, postdiv1);
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do_div(foutpostdiv, postdiv2);
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON0,
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PLL_BYPASS(0) | PLL_POSTDIV1(postdiv1) |
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PLL_FBDIV(fbdiv));
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON1,
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PLL_DSMPD(dsmpd) | PLL_POSTDIV2(postdiv2) |
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PLL_REFDIV(refdiv));
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON2, PLL_FRAC(frac));
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rk628_i2c_write(rk628, offset + CRU_CPLL_CON1, PLL_PD(0));
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while (1) {
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rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &val);
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if (val & PLL_LOCK)
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break;
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}
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return (unsigned long)foutpostdiv;
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}
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static unsigned long rk628_cru_clk_set_rate_sclk_vop(struct rk628 *rk628,
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unsigned long rate)
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{
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unsigned long m, n, parent_rate;
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u32 val;
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rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &val);
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val &= SCLK_VOP_SEL_MASK;
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val >>= SCLK_VOP_SEL_SHIFT;
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if (val == SCLK_VOP_SEL_GPLL)
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL);
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else
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL);
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rational_best_approximation(rate, parent_rate,
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GENMASK(15, 0), GENMASK(15, 0),
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&m, &n);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON13, m << 16 | n);
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return rate;
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}
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static unsigned long rk628_cru_clk_get_rate_sclk_vop(struct rk628 *rk628)
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{
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unsigned long rate, parent_rate, m, n;
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u32 mux, div;
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rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &mux);
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mux &= CLK_UART_SRC_SEL_MASK;
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mux >>= SCLK_VOP_SEL_SHIFT;
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if (mux == SCLK_VOP_SEL_GPLL)
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL);
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else
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL);
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rk628_i2c_read(rk628, CRU_CLKSEL_CON13, &div);
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m = div >> 16 & 0xffff;
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n = div & 0xffff;
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rate = parent_rate * m / n;
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return rate;
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}
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static unsigned long rk628_cru_clk_set_rate_rx_read(struct rk628 *rk628,
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unsigned long rate)
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{
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unsigned long m, n, parent_rate;
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u32 val;
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rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &val);
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val &= CLK_RX_READ_SEL_MASK;
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val >>= CLK_RX_READ_SEL_SHIFT;
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if (val == CLK_RX_READ_SEL_GPLL)
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL);
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else
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL);
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rational_best_approximation(rate, parent_rate,
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GENMASK(15, 0), GENMASK(15, 0),
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&m, &n);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON14, m << 16 | n);
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return rate;
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}
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static unsigned long rk628_cru_clk_get_rate_uart_src(struct rk628 *rk628)
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{
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unsigned long rate, parent_rate;
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u32 mux, div;
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rk628_i2c_read(rk628, CRU_CLKSEL_CON21, &mux);
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mux &= SCLK_VOP_SEL_MASK;
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if (mux == CLK_UART_SRC_SEL_GPLL)
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL);
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else
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL);
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rk628_i2c_read(rk628, CRU_CLKSEL_CON21, &div);
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div &= CLK_UART_SRC_DIV_MASK;
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div >>= CLK_UART_SRC_DIV_SHIFT;
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rate = parent_rate / (div + 1);
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return rate;
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}
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static unsigned long rk628_cru_clk_set_rate_sclk_uart(struct rk628 *rk628,
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unsigned long rate)
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{
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unsigned long m, n, parent_rate;
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parent_rate = rk628_cru_clk_get_rate_uart_src(rk628);
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if (rate == REFCLK_RATE) {
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rk628_i2c_write(rk628, CRU_CLKSEL_CON06,
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SCLK_UART_SEL(SCLK_UART_SEL_OSC));
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return rate;
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} else if (rate == parent_rate) {
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rk628_i2c_write(rk628, CRU_CLKSEL_CON06,
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SCLK_UART_SEL(SCLK_UART_SEL_UART_SRC));
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return rate;
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}
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rk628_i2c_write(rk628, CRU_CLKSEL_CON06,
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SCLK_UART_SEL(SCLK_UART_SEL_UART_FRAC));
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rational_best_approximation(rate, parent_rate,
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GENMASK(15, 0), GENMASK(15, 0),
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&m, &n);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON20, m << 16 | n);
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return rate;
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}
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static unsigned long
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rk628_cru_clk_get_rate_bt1120_dec_parent(struct rk628 *rk628)
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{
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unsigned long parent_rate;
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u32 mux;
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rk628_i2c_read(rk628, CRU_CLKSEL_CON02, &mux);
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mux &= CLK_BT1120DEC_SEL_MASK;
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if (mux == CLK_BT1120DEC_SEL_GPLL)
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_GPLL);
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else
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parent_rate = rk628_cru_clk_get_rate_pll(rk628, CGU_CLK_CPLL);
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return parent_rate;
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}
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static unsigned long rk628_cru_clk_set_rate_bt1120_dec(struct rk628 *rk628,
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unsigned long rate)
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{
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unsigned long parent_rate;
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u32 div;
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parent_rate = rk628_cru_clk_get_rate_bt1120_dec_parent(rk628);
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div = DIV_ROUND_UP(parent_rate, rate);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON02, CLK_BT1120DEC_DIV(div-1));
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return parent_rate / div;
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}
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int rk628_cru_clk_set_rate(struct rk628 *rk628, unsigned int id,
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unsigned long rate)
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{
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switch (id) {
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case CGU_CLK_CPLL:
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case CGU_CLK_GPLL:
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rk628_cru_clk_set_rate_pll(rk628, id, rate);
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break;
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case CGU_CLK_RX_READ:
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rk628_cru_clk_set_rate_rx_read(rk628, rate);
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break;
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case CGU_SCLK_VOP:
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rk628_cru_clk_set_rate_sclk_vop(rk628, rate);
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break;
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case CGU_SCLK_UART:
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rk628_cru_clk_set_rate_sclk_uart(rk628, rate);
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break;
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case CGU_BT1120DEC:
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rk628_cru_clk_set_rate_bt1120_dec(rk628, rate);
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break;
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default:
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return -1;
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}
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return 0;
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}
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unsigned long rk628_cru_clk_get_rate(struct rk628 *rk628, unsigned int id)
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{
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unsigned long rate;
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switch (id) {
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case CGU_CLK_CPLL:
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case CGU_CLK_GPLL:
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rate = rk628_cru_clk_get_rate_pll(rk628, id);
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break;
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case CGU_SCLK_VOP:
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rate = rk628_cru_clk_get_rate_sclk_vop(rk628);
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break;
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default:
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return 0;
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}
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return rate;
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}
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void rk628_cru_init(struct rk628 *rk628)
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{
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u32 val;
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u8 mcu_mode;
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rk628_i2c_read(rk628, GRF_SYSTEM_STATUS0, &val);
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mcu_mode = (val & I2C_ONLY_FLAG) ? 0 : 1;
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if (mcu_mode)
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return;
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rk628_i2c_write(rk628, CRU_GPLL_CON0, 0xffff701d);
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mdelay(1);
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rk628_i2c_write(rk628, CRU_MODE_CON00, 0xffff0004);
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mdelay(1);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff0080);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff0083);
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rk628_i2c_write(rk628, CRU_CPLL_CON0, 0xffff3063);
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mdelay(1);
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rk628_i2c_write(rk628, CRU_MODE_CON00, 0xffff0005);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff0003);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff000b);
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rk628_i2c_write(rk628, CRU_GPLL_CON0, 0xffff1028);
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mdelay(1);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff008b);
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rk628_i2c_write(rk628, CRU_CPLL_CON0, 0xffff1063);
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mdelay(1);
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rk628_i2c_write(rk628, CRU_CLKSEL_CON00, 0x00ff000b);
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}
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