435 lines
10 KiB
C
435 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chisp.com>
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*/
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#include "rk628.h"
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#include "rk628_combtxphy.h"
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#include "rk628_config.h"
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#include "rk628_csi.h"
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#define CSITX_ERR_RETRY_TIMES 3
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#define MIPI_DATARATE_MBPS_LOW 750
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#define MIPI_DATARATE_MBPS_HIGH 1250
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#define USE_4_LANES 4
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#define YUV422_8BIT 0x1e
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/* Test Code: 0x44 (HS RX Control of Lane 0) */
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#define HSFREQRANGE(x) UPDATE(x, 6, 1)
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struct rk628_csi {
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struct rk628_display_mode mode;
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bool txphy_pwron;
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u64 lane_mbps;
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};
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static inline void testif_testclk_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLK, PHY_TESTCLK);
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udelay(1);
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}
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static inline void testif_testclk_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLK, 0);
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udelay(1);
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}
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static inline void testif_testclr_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLR, PHY_TESTCLR);
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udelay(1);
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}
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static inline void testif_testclr_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTCLR, 0);
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udelay(1);
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}
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static inline void testif_testen_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTEN, PHY_TESTEN);
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udelay(1);
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}
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static inline void testif_testen_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTEN, 0);
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udelay(1);
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}
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static inline void testif_set_data(struct rk628 *rk628, u8 data)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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PHY_TESTDIN_MASK, PHY_TESTDIN(data));
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udelay(1);
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}
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static inline u8 testif_get_data(struct rk628 *rk628)
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{
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u32 data = 0;
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rk628_i2c_read(rk628, GRF_DPHY0_STATUS, &data);
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return data >> PHY_TESTDOUT_SHIFT;
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}
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static void testif_test_code_write(struct rk628 *rk628, u8 test_code)
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{
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testif_testclk_assert(rk628);
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testif_set_data(rk628, test_code);
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testif_testen_assert(rk628);
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testif_testclk_deassert(rk628);
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testif_testen_deassert(rk628);
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}
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static void testif_test_data_write(struct rk628 *rk628, u8 test_data)
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{
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testif_testclk_deassert(rk628);
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testif_set_data(rk628, test_data);
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testif_testclk_assert(rk628);
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}
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static u8 testif_write(struct rk628 *rk628, u8 test_code, u8 test_data)
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{
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u8 monitor_data;
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testif_test_code_write(rk628, test_code);
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testif_test_data_write(rk628, test_data);
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monitor_data = testif_get_data(rk628);
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dev_info(rk628->dev, "test_code=0x%02x, ", test_code);
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dev_info(rk628->dev, "test_data=0x%02x, ", test_data);
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dev_info(rk628->dev, "monitor_data=0x%02x\n", monitor_data);
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return monitor_data;
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}
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static void rk628_csi_get_detected_timings(struct rk628 *rk628)
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{
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struct rk628_display_mode *src, *dst;
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struct rk628_csi *csi = rk628->csi;
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if (!csi)
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return;
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src = rk628_display_get_src_mode(rk628);
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dst = rk628_display_get_dst_mode(rk628);
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rk628_set_output_bus_format(rk628, BUS_FMT_YUV422);
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rk628_mode_copy(dst, src);
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rk628_mode_copy(&csi->mode, dst);
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}
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static inline u8 testif_read(struct rk628 *rk628, u8 test_code)
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{
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u8 test_data;
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testif_test_code_write(rk628, test_code);
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test_data = testif_get_data(rk628);
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testif_test_data_write(rk628, test_data);
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return test_data;
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}
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static inline void mipi_dphy_enableclk_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, CSITX_DPHY_CTRL, DPHY_ENABLECLK,
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DPHY_ENABLECLK);
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udelay(1);
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}
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static inline void mipi_dphy_enableclk_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, CSITX_DPHY_CTRL, DPHY_ENABLECLK, 0);
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udelay(1);
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}
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static inline void mipi_dphy_shutdownz_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYSHUTDOWNZ, 0);
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udelay(1);
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}
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static inline void mipi_dphy_shutdownz_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYSHUTDOWNZ,
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CSI_PHYSHUTDOWNZ);
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udelay(1);
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}
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static inline void mipi_dphy_rstz_assert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYRSTZ, 0);
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udelay(1);
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}
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static inline void mipi_dphy_rstz_deassert(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON, CSI_PHYRSTZ,
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CSI_PHYRSTZ);
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udelay(1);
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}
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static void mipi_dphy_init_hsfreqrange(struct rk628 *rk628)
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{
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const struct {
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unsigned long max_lane_mbps;
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u8 hsfreqrange;
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} hsfreqrange_table[] = {
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{ 90, 0x00}, { 100, 0x10}, { 110, 0x20}, { 130, 0x01},
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{ 140, 0x11}, { 150, 0x21}, { 170, 0x02}, { 180, 0x12},
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{ 200, 0x22}, { 220, 0x03}, { 240, 0x13}, { 250, 0x23},
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{ 270, 0x04}, { 300, 0x14}, { 330, 0x05}, { 360, 0x15},
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{ 400, 0x25}, { 450, 0x06}, { 500, 0x16}, { 550, 0x07},
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{ 600, 0x17}, { 650, 0x08}, { 700, 0x18}, { 750, 0x09},
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{ 800, 0x19}, { 850, 0x29}, { 900, 0x39}, { 950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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u8 hsfreqrange;
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unsigned int index;
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struct rk628_csi *csi = rk628->csi;
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if (!csi)
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return;
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for (index = 0; index < ARRAY_SIZE(hsfreqrange_table); index++)
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if (csi->lane_mbps <= hsfreqrange_table[index].max_lane_mbps)
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break;
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if (index == ARRAY_SIZE(hsfreqrange_table))
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--index;
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hsfreqrange = hsfreqrange_table[index].hsfreqrange;
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testif_write(rk628, 0x44, HSFREQRANGE(hsfreqrange));
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}
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static int mipi_dphy_reset(struct rk628 *rk628)
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{
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u32 val;
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int ret;
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mipi_dphy_enableclk_deassert(rk628);
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mipi_dphy_shutdownz_assert(rk628);
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mipi_dphy_rstz_assert(rk628);
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testif_testclr_assert(rk628);
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/* Set all REQUEST inputs to zero */
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rk628_i2c_update_bits(rk628, GRF_MIPI_TX0_CON,
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FORCETXSTOPMODE_MASK | FORCERXMODE_MASK,
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FORCETXSTOPMODE(0) | FORCERXMODE(0));
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udelay(1);
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testif_testclr_deassert(rk628);
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mipi_dphy_enableclk_assert(rk628);
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mipi_dphy_shutdownz_deassert(rk628);
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mipi_dphy_rstz_deassert(rk628);
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usleep_range(1500, 2000);
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ret = rk628_i2c_read(rk628, CSITX_CSITX_STATUS1, &val);
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if (ret < 0) {
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dev_info(rk628->dev, "lane module is not in stop state\n");
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return ret;
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}
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return 0;
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}
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static int mipi_dphy_power_on(struct rk628 *rk628)
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{
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unsigned int val;
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u32 bus_width, mask;
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struct rk628_csi *csi = rk628->csi;
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if (!csi)
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return -1;
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if ((csi->mode.hdisplay == 3840) &&
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(csi->mode.vdisplay == 2160)) {
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csi->lane_mbps = MIPI_DATARATE_MBPS_HIGH;
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} else {
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csi->lane_mbps = MIPI_DATARATE_MBPS_LOW;
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}
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bus_width = csi->lane_mbps << 8;
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bus_width |= COMBTXPHY_MODULEA_EN;
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dev_info(rk628->dev, "%s mipi bitrate:%llu mbps\n", __func__, csi->lane_mbps);
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rk628_combtxphy_set_bus_width(rk628, bus_width);
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rk628_combtxphy_set_mode(rk628, PHY_MODE_VIDEO_MIPI);
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mipi_dphy_init_hsfreqrange(rk628);
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usleep_range(1500, 2000);
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rk628_combtxphy_power_on(rk628);
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usleep_range(1500, 2000);
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mask = DPHY_PLL_LOCK;
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rk628_i2c_read(rk628, CSITX_CSITX_STATUS1, &val);
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if ((val & mask) != mask) {
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dev_info(rk628->dev, "PHY is not locked\n");
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return -1;
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}
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udelay(10);
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return 0;
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}
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static void mipi_dphy_power_off(struct rk628 *rk628)
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{
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rk628_combtxphy_power_off(rk628);
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}
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static void rk62_csi_reset(struct rk628 *rk628)
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{
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rk628_i2c_write(rk628, CSITX_SYS_CTRL0_IMD, 0x1);
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usleep_range(1000, 1100);
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rk628_i2c_write(rk628, CSITX_SYS_CTRL0_IMD, 0x0);
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}
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static void rk628_csi_set_csi(struct rk628 *rk628)
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{
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u8 lanes = USE_4_LANES;
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u8 lane_num;
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u8 dphy_lane_en;
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u32 wc_usrdef;
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struct rk628_csi *csi;
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if (!rk628->csi) {
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csi = devm_kzalloc(rk628->dev, sizeof(*csi), GFP_KERNEL);
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if (!csi)
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return;
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rk628->csi = csi;
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} else {
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csi = rk628->csi;
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}
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lane_num = lanes - 1;
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dphy_lane_en = (1 << (lanes + 1)) - 1;
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wc_usrdef = csi->mode.hdisplay * 2;
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rk62_csi_reset(rk628);
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if (csi->txphy_pwron) {
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dev_info(rk628->dev, "%s: txphy already power on, power off\n",
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__func__);
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mipi_dphy_power_off(rk628);
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csi->txphy_pwron = false;
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}
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mipi_dphy_power_on(rk628);
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csi->txphy_pwron = true;
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dev_info(rk628->dev, "%s: txphy power on!\n", __func__);
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usleep_range(1000, 1500);
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rk628_i2c_update_bits(rk628, CSITX_CSITX_EN,
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VOP_UV_SWAP_MASK |
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VOP_YUV422_EN_MASK |
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VOP_P2_EN_MASK |
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LANE_NUM_MASK |
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DPHY_EN_MASK |
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CSITX_EN_MASK,
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VOP_UV_SWAP(1) |
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VOP_YUV422_EN(1) |
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VOP_P2_EN(1) |
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LANE_NUM(lane_num) |
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DPHY_EN(0) |
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CSITX_EN(0));
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rk628_i2c_update_bits(rk628, CSITX_SYS_CTRL1,
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BYPASS_SELECT_MASK,
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BYPASS_SELECT(1));
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rk628_i2c_write(rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
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rk628_i2c_write(rk628, CSITX_SYS_CTRL2, VOP_WHOLE_FRM_EN | VSYNC_ENABLE);
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rk628_i2c_update_bits(rk628, CSITX_SYS_CTRL3_IMD,
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CONT_MODE_CLK_CLR_MASK |
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CONT_MODE_CLK_SET_MASK |
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NON_CONTINOUS_MODE_MASK,
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CONT_MODE_CLK_CLR(0) |
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CONT_MODE_CLK_SET(0) |
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NON_CONTINOUS_MODE(1));
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rk628_i2c_write(rk628, CSITX_VOP_PATH_CTRL,
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VOP_WC_USERDEFINE(wc_usrdef) |
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VOP_DT_USERDEFINE(YUV422_8BIT) |
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VOP_PIXEL_FORMAT(0) |
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VOP_WC_USERDEFINE_EN(1) |
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VOP_DT_USERDEFINE_EN(1) |
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VOP_PATH_EN(1));
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rk628_i2c_update_bits(rk628, CSITX_DPHY_CTRL,
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CSI_DPHY_EN_MASK,
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CSI_DPHY_EN(dphy_lane_en));
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rk628_i2c_write(rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
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dev_info(rk628->dev, "%s csi cofig done\n", __func__);
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}
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static void enable_csitx(struct rk628 *rk628)
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{
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u32 i, ret, val;
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for (i = 0; i < CSITX_ERR_RETRY_TIMES; i++) {
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rk628_csi_set_csi(rk628);
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rk628_i2c_update_bits(rk628, CSITX_CSITX_EN,
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DPHY_EN_MASK |
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CSITX_EN_MASK,
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DPHY_EN(1) |
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CSITX_EN(1));
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rk628_i2c_write(rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
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msleep(40);
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rk628_i2c_write(rk628, CSITX_ERR_INTR_CLR_IMD, 0xffffffff);
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rk628_i2c_update_bits(rk628, CSITX_SYS_CTRL1,
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BYPASS_SELECT_MASK, BYPASS_SELECT(0));
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rk628_i2c_write(rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
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msleep(40);
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ret = rk628_i2c_read(rk628, CSITX_ERR_INTR_RAW_STATUS_IMD, &val);
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if (!ret && !val)
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break;
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dev_info(rk628->dev, "%s csitx err, retry:%d, err status:%#x, ret:%d\n",
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__func__, i, val, ret);
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}
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}
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static void enable_stream(struct rk628 *rk628, bool en)
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{
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dev_info(rk628->dev, "%s: %sable\n", __func__, en ? "en" : "dis");
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if (en) {
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enable_csitx(rk628);
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} else {
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rk628_i2c_update_bits(rk628, CSITX_CSITX_EN,
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DPHY_EN_MASK |
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CSITX_EN_MASK,
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DPHY_EN(0) |
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CSITX_EN(0));
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rk628_i2c_write(rk628, CSITX_CONFIG_DONE, CONFIG_DONE_IMD);
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}
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}
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void rk628_csi_init(struct rk628 *rk628)
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{
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rk628_i2c_update_bits(rk628, GRF_SYSTEM_CON0,
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SW_OUTPUT_MODE_MASK, SW_OUTPUT_MODE(OUTPUT_MODE_CSI));
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rk628_csi_get_detected_timings(rk628);
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mipi_dphy_reset(rk628);
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}
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void rk628_csi_enable(struct rk628 *rk628)
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{
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rk628_csi_get_detected_timings(rk628);
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return enable_stream(rk628, true);
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}
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void rk628_csi_disable(struct rk628 *rk628)
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{
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return enable_stream(rk628, false);
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}
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