297 lines
9.9 KiB
C
297 lines
9.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wyon Bi <bivvy.bi@rock-chips.com>
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*/
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#ifndef RK628_GPIO_H
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#define RK628_GPIO_H
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#define RK628_GPIO0_BASE 0x000D0000
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#define RK628_GPIO1_BASE 0x000E0000
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#define RK628_GPIO2_BASE 0x000F0000
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#define RK628_GPIO3_BASE 0x00100000
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#define RK628_GPIO_MAX_REGISTER (RK628_GPIO3_BASE + GPIO_VER_ID)
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/* GPIO control registers */
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#define GPIO_SWPORT_DR_L 0x00
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#define GPIO_SWPORT_DR_H 0x04
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#define GPIO_SWPORT_DDR_L 0x08
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#define GPIO_SWPORT_DDR_H 0x0c
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#define GPIO_INTEN_L 0x10
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#define GPIO_INTEN_H 0x14
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#define GPIO_INTMASK_L 0x18
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#define GPIO_INTMASK_H 0x1c
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#define GPIO_INTTYPE_L 0x20
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#define GPIO_INTTYPE_H 0x24
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#define GPIO_INT_POLARITY_L 0x28
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#define GPIO_INT_POLARITY_H 0x2c
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#define GPIO_INT_BOTHEDGE_L 0x30
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#define GPIO_INT_BOTHEDGE_H 0x34
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#define GPIO_DEBOUNCE_L 0x38
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#define GPIO_DEBOUNCE_H 0x3c
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#define GPIO_DBCLK_DIV_EN_L 0x40
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#define GPIO_DBCLK_DIV_EN_H 0x44
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#define GPIO_INT_STATUS 0x50
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#define GPIO_INT_RAWSTATUS 0x58
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#define GPIO_PORTS_EOI_L 0x60
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#define GPIO_PORTS_EOI_H 0x64
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#define GPIO_EXT_PORT 0x70
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#define GPIO_VER_ID 0x78
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#define GPIO_REG_LOW 0x0
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#define GPIO_REG_HIGH 0x1
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/* GPIO control registers */
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#define GPIO_INTMASK 0x34
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#define GPIO_PORTS_EOI 0x4c
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#define BANK_OFFSET 32
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#define GPIO_DIRECTION_OUT 1
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#define GPIO_DIRECTION_IN 0
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enum {
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GPIO_HIGH_Z,
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GPIO_PULL_UP,
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GPIO_PULL_DOWN,
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};
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enum {
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GPIO_BANK0 = 0,
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GPIO_BANK1,
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GPIO_BANK2,
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GPIO_BANK3,
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GPIO_BANKX = 9,
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};
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enum {
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GPIO0_A0 = BANK_OFFSET * 0,
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GPIO0_A1,
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GPIO0_A2,
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GPIO0_A3,
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GPIO0_A4,
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GPIO0_A5,
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GPIO0_A6,
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GPIO0_A7,
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GPIO0_B0,
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GPIO0_B1,
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GPIO0_B2,
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GPIO0_B3,
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GPIO1_A0 = BANK_OFFSET * 1,
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GPIO1_A1,
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GPIO1_A2,
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GPIO1_A3,
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GPIO1_A4,
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GPIO1_A5,
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GPIO1_A6,
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GPIO1_A7,
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GPIO1_B0,
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GPIO1_B1,
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GPIO1_B2,
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GPIO1_B3,
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GPIO1_B4,
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GPIO1_B5,
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GPIO2_A0 = BANK_OFFSET * 2,
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GPIO2_A1,
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GPIO2_A2,
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GPIO2_A3,
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GPIO2_A4,
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GPIO2_A5,
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GPIO2_A6,
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GPIO2_A7,
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GPIO2_B0,
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GPIO2_B1,
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GPIO2_B2,
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GPIO2_B3,
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GPIO2_B4,
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GPIO2_B5,
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GPIO2_B6,
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GPIO2_B7,
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GPIO2_C0,
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GPIO2_C1,
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GPIO2_C2,
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GPIO2_C3,
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GPIO2_C4,
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GPIO2_C5,
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GPIO2_C6,
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GPIO2_C7,
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GPIO3_A0 = BANK_OFFSET * 3,
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GPIO3_A1,
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GPIO3_A2,
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GPIO3_A3,
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GPIO3_A4,
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GPIO3_A5,
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GPIO3_A6,
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GPIO3_A7,
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GPIO3_B0,
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GPIO3_B1,
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GPIO3_B2,
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GPIO3_B3,
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GPIO3_B4,
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PIN_I2SM_SCK = BANK_OFFSET * 4 + 2,
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PIN_I2SM_D,
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PIN_I2SM_LR,
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PIN_RXDDC_SCL,
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PIN_RXDDC_SDA,
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PIN_HDMIRX_CE,
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PIN_JTAG_EN,
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PIN_UART_SEL,
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PIN_UART_RTS_EN,
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PIN_UART_CTS_EN,
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PIN_MUX,
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};
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struct rk628_pin_iomux_group {
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unsigned int pins;
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int bank;
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int mux;
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int iomux_base;
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int gpio_base;
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int pull_reg;
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};
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#define PINCTRL_GROUP(a, b, c, d, e, f) \
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{.pins = a, .bank = b, .mux = c, .iomux_base = d, .gpio_base = e, .pull_reg = f}
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static const struct rk628_pin_iomux_group rk628_pin_iomux_groups[] = {
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PINCTRL_GROUP(GPIO0_A0, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A1, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A2, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0),
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PINCTRL_GROUP(GPIO0_A3, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A4, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A5, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A6, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_A7, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON,
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RK628_GPIO0_BASE, GRF_GPIO0A_P_CON),
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PINCTRL_GROUP(GPIO0_B0, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0),
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PINCTRL_GROUP(GPIO0_B1, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0),
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PINCTRL_GROUP(GPIO0_B2, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0),
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PINCTRL_GROUP(GPIO0_B3, GPIO_BANK0, 1, GRF_GPIO0AB_SEL_CON, RK628_GPIO0_BASE, 0),
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PINCTRL_GROUP(GPIO1_A0, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A1, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A2, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A3, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A4, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A5, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A6, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_A7, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON,
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RK628_GPIO1_BASE, GRF_GPIO1A_P_CON),
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PINCTRL_GROUP(GPIO1_B0, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO1_B1, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO1_B2, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO1_B3, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO1_B4, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO1_B5, GPIO_BANK1, 1, GRF_GPIO1AB_SEL_CON, RK628_GPIO1_BASE, 0),
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PINCTRL_GROUP(GPIO2_A0, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A1, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A2, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A3, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A4, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A5, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A6, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_A7, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2A_P_CON),
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PINCTRL_GROUP(GPIO2_B0, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B1, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B2, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B3, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B4, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B5, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B6, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_B7, GPIO_BANK2, 1, GRF_GPIO2AB_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2B_P_CON),
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PINCTRL_GROUP(GPIO2_C0, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C1, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C2, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C3, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C4, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C5, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C6, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO2_C7, GPIO_BANK2, 1, GRF_GPIO2C_SEL_CON,
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RK628_GPIO2_BASE, GRF_GPIO2C_P_CON),
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PINCTRL_GROUP(GPIO3_A0, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3A_P_CON),
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PINCTRL_GROUP(GPIO3_A1, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3A_P_CON),
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PINCTRL_GROUP(GPIO3_A2, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3A_P_CON),
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PINCTRL_GROUP(GPIO3_A3, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3A_P_CON),
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PINCTRL_GROUP(GPIO3_A4, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, 0),
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PINCTRL_GROUP(GPIO3_A5, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, 0),
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PINCTRL_GROUP(GPIO3_A6, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, 0),
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PINCTRL_GROUP(GPIO3_A7, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, 0),
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PINCTRL_GROUP(GPIO3_B0, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3B_P_CON),
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PINCTRL_GROUP(GPIO3_B1, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3B_P_CON),
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PINCTRL_GROUP(GPIO3_B2, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3B_P_CON),
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PINCTRL_GROUP(GPIO3_B3, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3B_P_CON),
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PINCTRL_GROUP(GPIO3_B4, GPIO_BANK3, 1, GRF_GPIO3AB_SEL_CON,
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RK628_GPIO3_BASE, GRF_GPIO3B_P_CON),
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PINCTRL_GROUP(PIN_I2SM_SCK, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_I2SM_D, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_I2SM_LR, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_RXDDC_SCL, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_RXDDC_SDA, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_HDMIRX_CE, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_JTAG_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_UART_SEL, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_UART_RTS_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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PINCTRL_GROUP(PIN_UART_CTS_EN, GPIO_BANKX, 1, GRF_SYSTEM_CON3, 0, 0),
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};
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#endif // RK628_GPIO_H
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