233 lines
6.2 KiB
C
233 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd
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*
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* Authors:
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* Dingqiang Lin <jon.lin@rock-chips.com>
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*/
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#ifndef __UBOOT__
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#include <linux/device.h>
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#include <linux/kernel.h>
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#endif
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_UNIM_ZL 0xA1
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#define SPINAND_MFR_UNIM 0xB0
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static int tx25g01_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 8;
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region->length = 8;
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return 0;
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}
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static int tx25g01_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 2;
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region->length = 6;
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return 0;
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}
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static const struct mtd_ooblayout_ops tx25g01_ooblayout = {
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.ecc = tx25g01_ooblayout_ecc,
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.rfree = tx25g01_ooblayout_free,
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};
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static int um19a0xisw_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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return -ERANGE;
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}
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static int um19a0xisw_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = 62;
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return 0;
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}
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static const struct mtd_ooblayout_ops um19a0xisw_ooblayout = {
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.ecc = um19a0xisw_ooblayout_ecc,
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.rfree = um19a0xisw_ooblayout_free,
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};
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static int um19a1xisw_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 64;
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region->length = 64;
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return 0;
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}
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static int um19a1xisw_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = 62;
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return 0;
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}
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static const struct mtd_ooblayout_ops um19a1xisw_ooblayout = {
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.ecc = um19a1xisw_ooblayout_ecc,
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.rfree = um19a1xisw_ooblayout_free,
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};
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/*
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* ecc bits: 0xC0[4,6]
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* [0b000], No bit errors were detected;
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* [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0b100], Bit error count equals the bit flip
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* detection threshold
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* others, Reserved.
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*/
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static int tx25g01_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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u8 eccsr = (status & GENMASK(6, 4)) >> 4;
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if (eccsr < 4)
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return eccsr;
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else if (eccsr == 4)
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return nand->eccreq.strength;
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else
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return -EBADMSG;
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}
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/*
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* ecc bits: 0xC0[4,6]
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* [0b000], No bit errors were detected;
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* [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0b101], Bit error count equals the bit flip
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* detection threshold
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* [0b010], Multiple bit errors were detected and
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* not corrected.
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* others, Reserved.
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*/
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static int um19axxisw_ecc_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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u8 eccsr = (status & GENMASK(6, 4)) >> 4;
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if (eccsr <= 1 || eccsr == 3)
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return eccsr;
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else if (eccsr == 5)
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return nand->eccreq.strength;
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else
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return -EBADMSG;
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}
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static const struct spinand_info unim_zl_spinand_table[] = {
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SPINAND_INFO("TX25G01",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&tx25g01_ooblayout, tx25g01_ecc_get_status)),
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};
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static const struct spinand_info unim_spinand_table[] = {
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SPINAND_INFO("UM19A1HISW",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19axxisw_ecc_ecc_get_status)),
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SPINAND_INFO("UM19A0HCSW",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&um19a0xisw_ooblayout, um19axxisw_ecc_ecc_get_status)),
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SPINAND_INFO("UM19A0LCSW",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&um19a0xisw_ooblayout, um19axxisw_ecc_ecc_get_status)),
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SPINAND_INFO("UM19A1LISW",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&um19a1xisw_ooblayout, um19axxisw_ecc_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops unim_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer unim_zl_spinand_manufacturer = {
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.id = SPINAND_MFR_UNIM_ZL,
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.name = "UNIM_ZL",
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.chips = unim_zl_spinand_table,
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.nchips = ARRAY_SIZE(unim_zl_spinand_table),
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.ops = &unim_spinand_manuf_ops,
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};
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const struct spinand_manufacturer unim_spinand_manufacturer = {
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.id = SPINAND_MFR_UNIM,
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.name = "UNIM",
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.chips = unim_spinand_table,
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.nchips = ARRAY_SIZE(unim_spinand_table),
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.ops = &unim_spinand_manuf_ops,
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};
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