387 lines
11 KiB
C
387 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd
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*
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* Authors:
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* Dingqiang Lin <jon.lin@rock-chips.com>
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*/
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#ifndef __UBOOT__
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#include <linux/device.h>
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#include <linux/kernel.h>
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#endif
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#include <linux/mtd/spinand.h>
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#define SPINAND_MFR_XTX 0x0B
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static SPINAND_OP_VARIANTS(read_cache_variants,
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SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
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SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
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static SPINAND_OP_VARIANTS(write_cache_variants,
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SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
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SPINAND_PROG_LOAD(true, 0, NULL, 0));
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static SPINAND_OP_VARIANTS(update_cache_variants,
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SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
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SPINAND_PROG_LOAD(false, 0, NULL, 0));
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static int xt26g0xa_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 48;
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region->length = 16;
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return 0;
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}
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static int xt26g0xa_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = mtd->oobsize - 18;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26g0xa_ooblayout = {
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.ecc = xt26g0xa_ooblayout_ecc,
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.rfree = xt26g0xa_ooblayout_free,
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};
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static int xt26g01b_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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return -ERANGE;
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}
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static int xt26g01b_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = mtd->oobsize - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26g01b_ooblayout = {
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.ecc = xt26g01b_ooblayout_ecc,
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.rfree = xt26g01b_ooblayout_free,
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};
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static int xt26g02b_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 8;
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region->length = 8;
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return 0;
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}
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static int xt26g02b_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section > 3)
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return -ERANGE;
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region->offset = (16 * section) + 2;
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region->length = 6;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26g02b_ooblayout = {
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.ecc = xt26g02b_ooblayout_ecc,
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.rfree = xt26g02b_ooblayout_free,
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};
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static int xt26g01c_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = mtd->oobsize / 2;
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region->length = mtd->oobsize / 2;
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return 0;
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}
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static int xt26g01c_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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return -ERANGE;
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region->offset = 2;
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region->length = mtd->oobsize / 2 - 2;
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return 0;
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}
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static const struct mtd_ooblayout_ops xt26g01c_ooblayout = {
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.ecc = xt26g01c_ooblayout_ecc,
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.rfree = xt26g01c_ooblayout_free,
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};
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/*
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* ecc bits: 0xC0[2,5]
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* [0x0000], No bit errors were detected;
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* [0x0001, 0x0111], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0x1000], Multiple bit errors were detected and
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* not corrected.
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* [0x1100], Bit error count equals the bit flip
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* detectionthreshold
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* else, reserved
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*/
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static int xt26g0xa_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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u8 eccsr = (status & GENMASK(5, 2)) >> 2;
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if (eccsr <= 7)
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return eccsr;
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else if (eccsr == 12)
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return 8;
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else
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return -EBADMSG;
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}
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/*
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* ecc bits: 0xC0[4,6]
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* [0x0], No bit errors were detected;
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* [0x001, 0x011], Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0x100], Bit error count equals the bit flip
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* detectionthreshold
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* [0x101, 0x110], Reserved;
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* [0x111], Multiple bit errors were detected and
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* not corrected.
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*/
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static int xt26g02b_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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u8 eccsr = (status & GENMASK(6, 4)) >> 4;
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if (eccsr <= 4)
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return eccsr;
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else
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return -EBADMSG;
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}
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/*
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* ecc bits: 0xC0[4,7]
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* [0b0000], No bit errors were detected;
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* [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not
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* reach Flipping Bits;
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* [0b1000], 8 Bit errors were detected and corrected. Bit error count
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* equals the bit flip detectionthreshold;
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* [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected;
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* others, Reserved.
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*/
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static int xt26g01c_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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u8 eccsr = (status & GENMASK(7, 4)) >> 4;
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if (eccsr <= 8)
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return eccsr;
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else
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return -EBADMSG;
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}
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static int xt26g11c_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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struct nand_device *nand = spinand_to_nand(spinand);
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switch (status & STATUS_ECC_MASK) {
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case STATUS_ECC_NO_BITFLIPS:
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return 0;
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case STATUS_ECC_UNCOR_ERROR:
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return -EBADMSG;
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case STATUS_ECC_HAS_BITFLIPS:
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return 1;
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default:
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return nand->eccreq.strength;
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}
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return -EINVAL;
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}
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static const struct spinand_info xtx_spinand_table[] = {
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SPINAND_INFO("XT26G01A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G02A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE2),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G04A",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE3),
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NAND_MEMORG(1, 2048, 64, 128, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G01B",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xF1),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01b_ooblayout,
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xt26g0xa_ecc_get_status)),
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SPINAND_INFO("XT26G02B",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xF2),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(4, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g02b_ooblayout,
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xt26g02b_ecc_get_status)),
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SPINAND_INFO("XT26G01C",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x11),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout,
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xt26g01c_ecc_get_status)),
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SPINAND_INFO("XT26G02C",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x12),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g0xa_ooblayout,
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xt26g01c_ecc_get_status)),
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SPINAND_INFO("XT26G04C",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x13),
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout,
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xt26g01c_ecc_get_status)),
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SPINAND_INFO("XT26G11C",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x15),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout,
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xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26Q02DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
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NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26Q01DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
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NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26Q04DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53),
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26G01DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
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NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01b_ooblayout, xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26G02DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
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NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01b_ooblayout, xt26g11c_ecc_get_status)),
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SPINAND_INFO("XT26G04DWSIGA",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x33),
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NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
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NAND_ECCREQ(8, 512),
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SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
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};
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const struct spinand_manufacturer xtx_spinand_manufacturer = {
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.id = SPINAND_MFR_XTX,
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.name = "xtx",
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.chips = xtx_spinand_table,
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.nchips = ARRAY_SIZE(xtx_spinand_table),
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.ops = &xtx_spinand_manuf_ops,
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};
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