526 lines
13 KiB
C
526 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <dm.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/of_access.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/rockchip_smccc.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/sdram_common.h>
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#define DDR2_PARAMS_PHANDLE_NAME "ddr2_params"
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#define DDR3_PARAMS_PHANDLE_NAME "ddr3_params"
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#define DDR4_PARAMS_PHANDLE_NAME "ddr4_params"
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#define LPDDR2_PARAMS_PHANDLE_NAME "lpddr2_params"
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#define LPDDR3_PARAMS_PHANDLE_NAME "lpddr3_params"
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#define LPDDR4_PARAMS_PHANDLE_NAME "lpddr4_params"
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#define LPDDR4X_PARAMS_PHANDLE_NAME "lpddr4x_params"
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#define LPDDR5_PARAMS_PHANDLE_NAME "lpddr5_params"
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#define DTS_PAR_OFFSET (4096)
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#define PARAMS_INVALID_VAL (0xff00aa99)
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#define PARAMS_IGNORE_THIS (0)
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#define PMUGRF_OS_REG(n) (0x200 + (n) * 4)
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struct rk3326_ddr_de_skew_setting {
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unsigned int ca_de_skew[30];
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unsigned int cs0_de_skew[84];
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unsigned int cs1_de_skew[84];
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};
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/* there is a matching relationship, modify it with caution */
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static char *dmc_fsp_params[] = {
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"debug_print_level",
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"phy_de_skew_en",
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/* if need, add parameter after */
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};
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/* there is a matching relationship, modify it with caution */
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static char *ddr_params_v1[] = {
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/* version information V1.00 */
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"version",
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"expanded_version",
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"reserved",
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/* freq info, freq_0 is final frequency, unit: MHz */
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"freq_0",
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"freq_1",
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"freq_2",
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"freq_3",
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"freq_4",
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"freq_5",
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/* power save setting */
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"pd_idle",
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"sr_idle",
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"sr_mc_gate_idle",
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"srpd_lite_idle",
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"standby_idle",
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"pd_dis_freq",
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"sr_dis_freq",
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"dram_dll_dis_freq",
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"phy_dll_dis_freq",
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/* drv when odt on */
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"phy_dq_drv_odten",
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"phy_ca_drv_odten",
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"phy_clk_drv_odten",
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"dram_dq_drv_odten",
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/* drv when odt off */
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"phy_dq_drv_odtoff",
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"phy_ca_drv_odtoff",
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"phy_clk_drv_odtoff",
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"dram_dq_drv_odtoff",
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/* odt info */
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"dram_odt",
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"phy_odt",
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"phy_odt_puup_en",
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"phy_odt_pudn_en",
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/* odt enable freq */
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"dram_dq_odt_en_freq",
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"phy_odt_en_freq",
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/* slew rate when odt enable */
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"phy_dq_sr_odten",
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"phy_ca_sr_odten",
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"phy_clk_sr_odten",
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/* slew rate when odt disable */
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"phy_dq_sr_odtoff",
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"phy_ca_sr_odtoff",
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"phy_clk_sr_odtoff",
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/* ssmod setting*/
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"ssmod_downspread",
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"ssmod_div",
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"ssmod_spread",
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/* 2T mode */
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"mode_2t",
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/* speed bin */
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"speed_bin",
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/* dram extended temperature support */
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"dram_ext_temp",
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/* byte map */
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"byte_map",
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/* dq map */
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"dq_map_cs0_dq_l",
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"dq_map_cs0_dq_h",
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"dq_map_cs1_dq_l",
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"dq_map_cs1_dq_h",
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/* for LPDDR4 and LPDDR4X */
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/* odt info */
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"lp4_ca_odt",
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"lp4_drv_pu_cal_odten",
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"lp4_drv_pu_cal_odtoff",
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"phy_lp4_drv_pulldown_en_odten",
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"phy_lp4_drv_pulldown_en_odtoff",
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/* odt enable freq */
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"lp4_ca_odt_en_freq",
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/* lp4 cs drv info and ca odt info */
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"phy_lp4_cs_drv_odten",
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"phy_lp4_cs_drv_odtoff",
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"lp4_odte_ck_en",
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"lp4_odte_cs_en",
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"lp4_odtd_ca_en",
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/* lp4 vref info when odt enable */
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"phy_lp4_dq_vref_odten",
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"lp4_dq_vref_odten",
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"lp4_ca_vref_odten",
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/* lp4 vref info when odt disable */
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"phy_lp4_dq_vref_odtoff",
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"lp4_dq_vref_odtoff",
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"lp4_ca_vref_odtoff",
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/* if need, add parameter after and change the minor version. */
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};
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/* the expanded version V1.00 add skew info */
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static char *ddr_params_exp_v1[] = {
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"ddr3a1_ddr4a9_de-skew",
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"ddr3a0_ddr4a10_de-skew",
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"ddr3a3_ddr4a6_de-skew",
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"ddr3a2_ddr4a4_de-skew",
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"ddr3a5_ddr4a8_de-skew",
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"ddr3a4_ddr4a5_de-skew",
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"ddr3a7_ddr4a11_de-skew",
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"ddr3a6_ddr4a7_de-skew",
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"ddr3a9_ddr4a0_de-skew",
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"ddr3a8_ddr4a13_de-skew",
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"ddr3a11_ddr4a3_de-skew",
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"ddr3a10_ddr4cs0_de-skew",
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"ddr3a13_ddr4a2_de-skew",
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"ddr3a12_ddr4ba1_de-skew",
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"ddr3a15_ddr4odt0_de-skew",
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"ddr3a14_ddr4a1_de-skew",
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"ddr3ba1_ddr4a15_de-skew",
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"ddr3ba0_ddr4bg0_de-skew",
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"ddr3ras_ddr4cke_de-skew",
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"ddr3ba2_ddr4ba0_de-skew",
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"ddr3we_ddr4bg1_de-skew",
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"ddr3cas_ddr4a12_de-skew",
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"ddr3ckn_ddr4ckn_de-skew",
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"ddr3ckp_ddr4ckp_de-skew",
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"ddr3cke_ddr4a16_de-skew",
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"ddr3odt0_ddr4a14_de-skew",
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"ddr3cs0_ddr4act_de-skew",
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"ddr3reset_ddr4reset_de-skew",
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"ddr3cs1_ddr4cs1_de-skew",
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"ddr3odt1_ddr4odt1_de-skew",
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"cs0_dm0_rx_de-skew",
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"cs0_dm0_tx_de-skew",
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"cs0_dq0_rx_de-skew",
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"cs0_dq0_tx_de-skew",
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"cs0_dq1_rx_de-skew",
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"cs0_dq1_tx_de-skew",
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"cs0_dq2_rx_de-skew",
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"cs0_dq2_tx_de-skew",
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"cs0_dq3_rx_de-skew",
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"cs0_dq3_tx_de-skew",
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"cs0_dq4_rx_de-skew",
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"cs0_dq4_tx_de-skew",
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"cs0_dq5_rx_de-skew",
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"cs0_dq5_tx_de-skew",
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"cs0_dq6_rx_de-skew",
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"cs0_dq6_tx_de-skew",
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"cs0_dq7_rx_de-skew",
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"cs0_dq7_tx_de-skew",
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"cs0_dqs0_rx_de-skew",
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"cs0_dqs0p_tx_de-skew",
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"cs0_dqs0n_tx_de-skew",
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"cs0_dm1_rx_de-skew",
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"cs0_dm1_tx_de-skew",
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"cs0_dq8_rx_de-skew",
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"cs0_dq8_tx_de-skew",
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"cs0_dq9_rx_de-skew",
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"cs0_dq9_tx_de-skew",
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"cs0_dq10_rx_de-skew",
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"cs0_dq10_tx_de-skew",
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"cs0_dq11_rx_de-skew",
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"cs0_dq11_tx_de-skew",
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"cs0_dq12_rx_de-skew",
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"cs0_dq12_tx_de-skew",
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"cs0_dq13_rx_de-skew",
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"cs0_dq13_tx_de-skew",
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"cs0_dq14_rx_de-skew",
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"cs0_dq14_tx_de-skew",
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"cs0_dq15_rx_de-skew",
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"cs0_dq15_tx_de-skew",
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"cs0_dqs1_rx_de-skew",
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"cs0_dqs1p_tx_de-skew",
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"cs0_dqs1n_tx_de-skew",
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"cs0_dm2_rx_de-skew",
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"cs0_dm2_tx_de-skew",
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"cs0_dq16_rx_de-skew",
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"cs0_dq16_tx_de-skew",
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"cs0_dq17_rx_de-skew",
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"cs0_dq17_tx_de-skew",
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"cs0_dq18_rx_de-skew",
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"cs0_dq18_tx_de-skew",
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"cs0_dq19_rx_de-skew",
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"cs0_dq19_tx_de-skew",
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"cs0_dq20_rx_de-skew",
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"cs0_dq20_tx_de-skew",
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"cs0_dq21_rx_de-skew",
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"cs0_dq21_tx_de-skew",
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"cs0_dq22_rx_de-skew",
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"cs0_dq22_tx_de-skew",
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"cs0_dq23_rx_de-skew",
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"cs0_dq23_tx_de-skew",
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"cs0_dqs2_rx_de-skew",
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"cs0_dqs2p_tx_de-skew",
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"cs0_dqs2n_tx_de-skew",
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"cs0_dm3_rx_de-skew",
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"cs0_dm3_tx_de-skew",
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"cs0_dq24_rx_de-skew",
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"cs0_dq24_tx_de-skew",
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"cs0_dq25_rx_de-skew",
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"cs0_dq25_tx_de-skew",
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"cs0_dq26_rx_de-skew",
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"cs0_dq26_tx_de-skew",
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"cs0_dq27_rx_de-skew",
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"cs0_dq27_tx_de-skew",
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"cs0_dq28_rx_de-skew",
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"cs0_dq28_tx_de-skew",
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"cs0_dq29_rx_de-skew",
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"cs0_dq29_tx_de-skew",
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"cs0_dq30_rx_de-skew",
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"cs0_dq30_tx_de-skew",
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"cs0_dq31_rx_de-skew",
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"cs0_dq31_tx_de-skew",
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"cs0_dqs3_rx_de-skew",
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"cs0_dqs3p_tx_de-skew",
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"cs0_dqs3n_tx_de-skew",
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"cs1_dm0_rx_de-skew",
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"cs1_dm0_tx_de-skew",
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"cs1_dq0_rx_de-skew",
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"cs1_dq0_tx_de-skew",
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"cs1_dq1_rx_de-skew",
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"cs1_dq1_tx_de-skew",
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"cs1_dq2_rx_de-skew",
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"cs1_dq2_tx_de-skew",
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"cs1_dq3_rx_de-skew",
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"cs1_dq3_tx_de-skew",
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"cs1_dq4_rx_de-skew",
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"cs1_dq4_tx_de-skew",
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"cs1_dq5_rx_de-skew",
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"cs1_dq5_tx_de-skew",
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"cs1_dq6_rx_de-skew",
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"cs1_dq6_tx_de-skew",
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"cs1_dq7_rx_de-skew",
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"cs1_dq7_tx_de-skew",
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"cs1_dqs0_rx_de-skew",
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"cs1_dqs0p_tx_de-skew",
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"cs1_dqs0n_tx_de-skew",
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"cs1_dm1_rx_de-skew",
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"cs1_dm1_tx_de-skew",
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"cs1_dq8_rx_de-skew",
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"cs1_dq8_tx_de-skew",
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"cs1_dq9_rx_de-skew",
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"cs1_dq9_tx_de-skew",
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"cs1_dq10_rx_de-skew",
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"cs1_dq10_tx_de-skew",
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"cs1_dq11_rx_de-skew",
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"cs1_dq11_tx_de-skew",
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"cs1_dq12_rx_de-skew",
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"cs1_dq12_tx_de-skew",
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"cs1_dq13_rx_de-skew",
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"cs1_dq13_tx_de-skew",
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"cs1_dq14_rx_de-skew",
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"cs1_dq14_tx_de-skew",
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"cs1_dq15_rx_de-skew",
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"cs1_dq15_tx_de-skew",
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"cs1_dqs1_rx_de-skew",
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"cs1_dqs1p_tx_de-skew",
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"cs1_dqs1n_tx_de-skew",
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"cs1_dm2_rx_de-skew",
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"cs1_dm2_tx_de-skew",
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"cs1_dq16_rx_de-skew",
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"cs1_dq16_tx_de-skew",
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"cs1_dq17_rx_de-skew",
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"cs1_dq17_tx_de-skew",
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"cs1_dq18_rx_de-skew",
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"cs1_dq18_tx_de-skew",
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"cs1_dq19_rx_de-skew",
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"cs1_dq19_tx_de-skew",
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"cs1_dq20_rx_de-skew",
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"cs1_dq20_tx_de-skew",
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"cs1_dq21_rx_de-skew",
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"cs1_dq21_tx_de-skew",
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"cs1_dq22_rx_de-skew",
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"cs1_dq22_tx_de-skew",
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"cs1_dq23_rx_de-skew",
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"cs1_dq23_tx_de-skew",
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"cs1_dqs2_rx_de-skew",
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"cs1_dqs2p_tx_de-skew",
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"cs1_dqs2n_tx_de-skew",
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"cs1_dm3_rx_de-skew",
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"cs1_dm3_tx_de-skew",
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"cs1_dq24_rx_de-skew",
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"cs1_dq24_tx_de-skew",
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"cs1_dq25_rx_de-skew",
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"cs1_dq25_tx_de-skew",
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"cs1_dq26_rx_de-skew",
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"cs1_dq26_tx_de-skew",
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"cs1_dq27_rx_de-skew",
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"cs1_dq27_tx_de-skew",
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"cs1_dq28_rx_de-skew",
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"cs1_dq28_tx_de-skew",
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"cs1_dq29_rx_de-skew",
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"cs1_dq29_tx_de-skew",
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"cs1_dq30_rx_de-skew",
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"cs1_dq30_tx_de-skew",
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"cs1_dq31_rx_de-skew",
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"cs1_dq31_tx_de-skew",
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"cs1_dqs3_rx_de-skew",
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"cs1_dqs3p_tx_de-skew",
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"cs1_dqs3n_tx_de-skew",
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};
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static int get_atf_version(void)
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{
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struct arm_smccc_res res;
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res = sip_smc_dram(0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
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if (res.a0)
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return -ENOMEM;
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else
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return res.a1;
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}
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static int dmc_fsp_probe(struct udevice *dev)
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{
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struct device_node *np_params, *np_tim;
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struct arm_smccc_res res;
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void *pmugrf_base;
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int *p = NULL;
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char *phandle_name = NULL;
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char **ddr_params;
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char **ddr_params_exp;
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int ddr_params_version;
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int expanded_version;
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u32 dram_type, os_reg2_val, os_reg3_val;
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u32 phy_de_skew_en;
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u32 i = 0, count = 0, size = 0, count_exp = 0;
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ulong atf_version_limit;
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atf_version_limit = dev_get_driver_data(dev);
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if (get_atf_version() < atf_version_limit) {
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printf("%s: trusted firmware need to update or is invalid!\n", __func__);
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printf("%s: current ATF version 0x%x, required version 0x%lx\n",
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__func__, get_atf_version(), atf_version_limit);
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return 0;
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}
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pmugrf_base = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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os_reg2_val = readl(pmugrf_base + PMUGRF_OS_REG(2));
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os_reg3_val = readl(pmugrf_base + PMUGRF_OS_REG(3));
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dram_type = SYS_REG_DEC_DDRTYPE_V3(os_reg2_val, os_reg3_val);
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if (dram_type == DDR2)
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phandle_name = DDR2_PARAMS_PHANDLE_NAME;
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else if (dram_type == DDR3)
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phandle_name = DDR3_PARAMS_PHANDLE_NAME;
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else if (dram_type == DDR4)
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phandle_name = DDR4_PARAMS_PHANDLE_NAME;
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else if (dram_type == LPDDR2)
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phandle_name = LPDDR2_PARAMS_PHANDLE_NAME;
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else if (dram_type == LPDDR3)
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phandle_name = LPDDR3_PARAMS_PHANDLE_NAME;
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else if (dram_type == LPDDR4)
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phandle_name = LPDDR4_PARAMS_PHANDLE_NAME;
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else if (dram_type == LPDDR4X)
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phandle_name = LPDDR4X_PARAMS_PHANDLE_NAME;
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else if (dram_type == LPDDR5)
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phandle_name = LPDDR5_PARAMS_PHANDLE_NAME;
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else
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printf("%s: dram_type unsupported\n", __func__);
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np_params = of_parse_phandle(ofnode_to_np(dev_ofnode(dev)), phandle_name, 0);
|
|
if (!np_params) {
|
|
printf("%s: of_parse_phandle %s error!\n", __func__, phandle_name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ddr_params_version = ofnode_read_u32_default(np_to_ofnode(np_params), "version", -1);
|
|
if (ddr_params_version < 0) {
|
|
printf("%s: get ddr_params_version error\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((ddr_params_version & 0xff00) == 0x100 &&
|
|
(ddr_params_version & 0xffff) <= 0x101) {
|
|
count = ARRAY_SIZE(ddr_params_v1);
|
|
ddr_params = ddr_params_v1;
|
|
} else {
|
|
printf("%s: ddr_params_version=0x%x unsupported\n", __func__, ddr_params_version);
|
|
return -EINVAL;
|
|
}
|
|
|
|
expanded_version = ofnode_read_u32_default(np_to_ofnode(np_params),
|
|
"expanded_version", 0);
|
|
if (expanded_version != PARAMS_IGNORE_THIS) {
|
|
if ((expanded_version & 0xff00) == 0x100 &&
|
|
(expanded_version & 0xffff) <= 0x100) {
|
|
count_exp = ARRAY_SIZE(ddr_params_exp_v1);
|
|
ddr_params_exp = ddr_params_exp_v1;
|
|
} else {
|
|
printf("expanded_version=0x%x unsupported\n",
|
|
expanded_version);
|
|
return -1;
|
|
}
|
|
} else if ((ddr_params_version & 0xffff) == 0x101) {
|
|
count_exp = ARRAY_SIZE(ddr_params_exp_v1);
|
|
}
|
|
/*
|
|
* page 0 is used for share param
|
|
* page 1~N is used for dmc_fsp and ddr_params_exp param
|
|
*/
|
|
size = ((count + count_exp) * 4 + 4096);
|
|
res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1, SHARE_PAGE_TYPE_DDRFSP);
|
|
if (res.a0 != 0) {
|
|
printf("%s:no share memory for init\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* fill share memory and pass to the atf */
|
|
p = (int *)(res.a1);
|
|
for (i = 0; i < ARRAY_SIZE(dmc_fsp_params); i++)
|
|
p[i] = dev_read_u32_default(dev, dmc_fsp_params[i], PARAMS_INVALID_VAL);
|
|
|
|
phy_de_skew_en = p[1];
|
|
|
|
p = (int *)(res.a1 + DTS_PAR_OFFSET / 4);
|
|
for (i = 0; i < ARRAY_SIZE(ddr_params_v1); i++) {
|
|
p[i] = ofnode_read_u32_default(np_to_ofnode(np_params), ddr_params[i],
|
|
PARAMS_INVALID_VAL);
|
|
}
|
|
|
|
if (expanded_version != PARAMS_IGNORE_THIS) {
|
|
if ((expanded_version & 0xff00) == 0x100 &&
|
|
(expanded_version & 0xffff) <= 0x100) {
|
|
phandle_name = "ddr_timing";
|
|
np_tim =
|
|
of_parse_phandle(ofnode_to_np(dev_ofnode(dev)),
|
|
phandle_name, 0);
|
|
if (!np_tim) {
|
|
printf("%s: of_parse_phandle %s error!\n",
|
|
__func__, phandle_name);
|
|
return -EINVAL;
|
|
}
|
|
for (i = count; i < (count + count_exp); i++) {
|
|
p[i] =
|
|
ofnode_read_u32_default(np_to_ofnode(np_tim),
|
|
ddr_params_exp[i -
|
|
count],
|
|
PARAMS_INVALID_VAL);
|
|
}
|
|
/* expanded_version and start point */
|
|
p[1] = (p[1] & 0xffff) | (count << 16);
|
|
}
|
|
} else if (phy_de_skew_en && (phy_de_skew_en != PARAMS_INVALID_VAL)) {
|
|
phandle_name = "ddr_timing";
|
|
np_tim = of_parse_phandle(ofnode_to_np(dev_ofnode(dev)), phandle_name, 0);
|
|
if (!np_tim) {
|
|
printf("%s: of_parse_phandle %s error!\n", __func__, phandle_name);
|
|
return -EINVAL;
|
|
}
|
|
for (i = count;
|
|
i < (count + ARRAY_SIZE(ddr_params_exp_v1)); i++) {
|
|
p[i] =
|
|
ofnode_read_u32_default(np_to_ofnode(np_tim),
|
|
ddr_params_exp_v1[i - count],
|
|
PARAMS_INVALID_VAL);
|
|
}
|
|
}
|
|
|
|
flush_cache((unsigned long)(res.a1), (DIV_ROUND_UP(size, 4096) + 1) * 0x1000);
|
|
res = sip_smc_dram(SHARE_PAGE_TYPE_DDRFSP, 0, ROCKCHIP_SIP_CONFIG_DRAM_FSP_INIT);
|
|
if (res.a0) {
|
|
printf("%s: rockchip_sip_config_dram_fsp_init error:%lx\n", __func__, res.a0);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id rockchip_dmc_fsp_ids[] = {
|
|
{ .compatible = "rockchip,rk3568-dmc-fsp", .data = 0x102},
|
|
{ .compatible = "rockchip,px30s-dmc-fsp", .data = 0x106},
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(dmc_fsp) = {
|
|
.name = "rockchip_dmc_fsp",
|
|
.id = UCLASS_DMC,
|
|
.probe = dmc_fsp_probe,
|
|
.of_match = rockchip_dmc_fsp_ids,
|
|
};
|