95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef XLAT_MMU_HELPERS_H
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#define XLAT_MMU_HELPERS_H
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/*
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* The following flags are passed to enable_mmu_xxx() to override the default
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* values used to program system registers while enabling the MMU.
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*/
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/*
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* When this flag is used, all data access to Normal memory from this EL and all
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* Normal memory accesses to the translation tables of this EL are non-cacheable
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* for all levels of data and unified cache until the caches are enabled by
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* setting the bit SCTLR_ELx.C.
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*/
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#define DISABLE_DCACHE (U(1) << 0)
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/*
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* Mark the translation tables as non-cacheable for the MMU table walker, which
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* is a different observer from the PE/CPU. If the flag is not specified, the
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* tables are cacheable for the MMU table walker.
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*
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* Note that, as far as the PE/CPU observer is concerned, the attributes used
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* are the ones specified in the translation tables themselves. The MAIR
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* register specifies the cacheability through the field AttrIndx of the lower
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* attributes of the translation tables. The shareability is specified in the SH
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* field of the lower attributes.
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*
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* The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn
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* and SHn of the TCR register to access the translation tables.
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*
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* The attributes specified in the TCR register and the tables can be different
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* as there are no checks to prevent that. Special care must be taken to ensure
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* that there aren't mismatches. The behaviour in that case is described in the
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* sections 'Mismatched memory attributes' in the ARMv8 ARM.
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*/
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#define XLAT_TABLE_NC (U(1) << 1)
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/*
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* Offsets into a mmu_cfg_params array generated by setup_mmu_cfg(). All
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* parameters are 64 bits wide.
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*/
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#define MMU_CFG_MAIR 0
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#define MMU_CFG_TCR 1
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#define MMU_CFG_TTBR0 2
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#define MMU_CFG_PARAM_MAX 3
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#ifndef __ASSEMBLER__
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#include <arch_helpers.h>
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/*
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* Return the values that the MMU configuration registers must contain for the
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* specified translation context. `params` must be a pointer to array of size
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* MMU_CFG_PARAM_MAX.
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*/
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void setup_mmu_cfg(uint64_t *params, unsigned int flags,
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const uint64_t *base_table, unsigned long long max_pa,
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uintptr_t max_va, int xlat_regime);
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#ifdef __aarch64__
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/* AArch64 specific translation table APIs */
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void enable_mmu_el1(unsigned int flags);
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void enable_mmu_el2(unsigned int flags);
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void enable_mmu_el3(unsigned int flags);
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void enable_mmu(unsigned int flags);
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void enable_mmu_direct_el1(unsigned int flags);
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void enable_mmu_direct_el2(unsigned int flags);
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void enable_mmu_direct_el3(unsigned int flags);
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#else
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/* AArch32 specific translation table API */
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void enable_mmu_svc_mon(unsigned int flags);
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void enable_mmu_hyp(unsigned int flags);
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void enable_mmu_direct_svc_mon(unsigned int flags);
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void enable_mmu_direct_hyp(unsigned int flags);
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#endif /* __aarch64__ */
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bool xlat_arch_is_granule_size_supported(size_t size);
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size_t xlat_arch_get_max_supported_granule_size(void);
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#endif /* __ASSEMBLER__ */
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#endif /* XLAT_MMU_HELPERS_H */
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