183 lines
6.3 KiB
C
183 lines
6.3 KiB
C
/*
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef XLAT_TABLES_DEFS_H
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#define XLAT_TABLES_DEFS_H
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#include <arch.h>
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#include <lib/utils_def.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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/* Miscellaneous MMU related constants */
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#define NUM_2MB_IN_GB (U(1) << 9)
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#define NUM_4K_IN_2MB (U(1) << 9)
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#define NUM_GB_IN_4GB (U(1) << 2)
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#define TWO_MB_SHIFT U(21)
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#define ONE_GB_SHIFT U(30)
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#define FOUR_KB_SHIFT U(12)
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#define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT)
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#define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT)
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#define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT)
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#define PAGE_SIZE_4KB U(4096)
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#define PAGE_SIZE_16KB U(16384)
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#define PAGE_SIZE_64KB U(65536)
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#define INVALID_DESC U(0x0)
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/*
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* A block descriptor points to a region of memory bigger than the granule size
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* (e.g. a 2MB region when the granule size is 4KB).
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*/
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#define BLOCK_DESC U(0x1) /* Table levels 0-2 */
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/* A table descriptor points to the next level of translation table. */
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#define TABLE_DESC U(0x3) /* Table levels 0-2 */
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/*
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* A page descriptor points to a page, i.e. a memory region whose size is the
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* translation granule size (e.g. 4KB).
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*/
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#define PAGE_DESC U(0x3) /* Table level 3 */
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#define DESC_MASK U(0x3)
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#define FIRST_LEVEL_DESC_N ONE_GB_SHIFT
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#define SECOND_LEVEL_DESC_N TWO_MB_SHIFT
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#define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT
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/* XN: Translation regimes that support one VA range (EL2 and EL3). */
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#define XN (ULL(1) << 2)
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/* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */
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#define UXN (ULL(1) << 2)
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#define PXN (ULL(1) << 1)
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#define CONT_HINT (ULL(1) << 0)
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#define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52)
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#define NON_GLOBAL (U(1) << 9)
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#define ACCESS_FLAG (U(1) << 8)
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#define NSH (U(0x0) << 6)
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#define OSH (U(0x2) << 6)
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#define ISH (U(0x3) << 6)
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#ifdef __aarch64__
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/* Guarded Page bit */
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#define GP (ULL(1) << 50)
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#endif
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#define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000)
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/*
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* The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or
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* 64KB. However, only 4KB are supported at the moment.
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*/
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#define PAGE_SIZE_SHIFT FOUR_KB_SHIFT
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#define PAGE_SIZE (UL(1) << PAGE_SIZE_SHIFT)
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#define PAGE_SIZE_MASK (PAGE_SIZE - UL(1))
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#define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == U(0))
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#if (ARM_ARCH_MAJOR == 7) && !ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING
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#define XLAT_ENTRY_SIZE_SHIFT U(2) /* Each MMU table entry is 4 bytes */
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#else
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#define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes */
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#endif
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#define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */
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#define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT)
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#define XLAT_TABLE_LEVEL_MAX U(3)
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/* Values for number of entries in each MMU translation table */
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#define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT)
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#define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - U(1))
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/* Values to convert a memory address to an index into a translation table */
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#define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT
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#define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT)
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#define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \
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((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT))
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#define XLAT_BLOCK_SIZE(level) (UL(1) << XLAT_ADDR_SHIFT(level))
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/* Mask to get the bits used to index inside a block of a certain level */
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#define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - UL(1))
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/* Mask to get the address bits common to a block of a certain table level*/
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#define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level))
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/*
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* Extract from the given virtual address the index into the given lookup level.
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* This macro assumes the system is using the 4KB translation granule.
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*/
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#define XLAT_TABLE_IDX(virtual_addr, level) \
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(((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF))
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/*
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* The ARMv8 translation table descriptor format defines AP[2:1] as the Access
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* Permissions bits, and does not define an AP[0] bit.
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*
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* AP[1] is valid only for a stage 1 translation that supports two VA ranges
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* (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). It is RES1
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* when stage 1 translations can only support one VA range.
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*/
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#define AP2_SHIFT U(0x7)
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#define AP2_RO ULL(0x1)
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#define AP2_RW ULL(0x0)
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#define AP1_SHIFT U(0x6)
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#define AP1_ACCESS_UNPRIVILEGED ULL(0x1)
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#define AP1_NO_ACCESS_UNPRIVILEGED ULL(0x0)
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#define AP1_RES1 ULL(0x1)
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/*
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* The following definitions must all be passed to the LOWER_ATTRS() macro to
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* get the right bitmask.
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*/
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#define AP_RO (AP2_RO << 5)
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#define AP_RW (AP2_RW << 5)
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#define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4)
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#define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4)
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#define AP_ONE_VA_RANGE_RES1 (AP1_RES1 << 4)
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#define NS (U(0x1) << 3)
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#define ATTR_NON_CACHEABLE_INDEX ULL(0x2)
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#define ATTR_DEVICE_INDEX ULL(0x1)
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#define ATTR_IWBWA_OWBWA_NTR_INDEX ULL(0x0)
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#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
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/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
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#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
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/* Device-nGnRE */
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#define ATTR_DEVICE MAIR_DEV_nGnRE
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/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
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#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
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#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define ATTR_INDEX_MASK U(0x3)
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#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)
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/*
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* Shift values for the attributes fields in a block or page descriptor.
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* See section D4.3.3 in the ARMv8-A ARM (issue B.a).
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*/
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/* Memory attributes index field, AttrIndx[2:0]. */
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#define ATTR_INDEX_SHIFT 2
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/* Non-secure bit, NS. */
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#define NS_SHIFT 5
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/* Shareability field, SH[1:0] */
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#define SHAREABILITY_SHIFT 8
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/* The Access Flag, AF. */
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#define ACCESS_FLAG_SHIFT 10
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/* The not global bit, nG. */
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#define NOT_GLOBAL_SHIFT 11
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/* Contiguous hint bit. */
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#define CONT_HINT_SHIFT 52
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/* Execute-never bits, XN. */
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#define PXN_SHIFT 53
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#define XN_SHIFT 54
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#define UXN_SHIFT XN_SHIFT
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#endif /* XLAT_TABLES_DEFS_H */
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