105 lines
2.5 KiB
ArmAsm
105 lines
2.5 KiB
ArmAsm
/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ARM_MACROS_S
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#define ARM_MACROS_S
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv2.h>
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#include <drivers/arm/gicv3.h>
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#include <platform_def.h>
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.section .rodata.gic_reg_name, "aS"
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/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
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gicc_regs:
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.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
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/* Applicable only to GICv3 with SRE enabled */
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icc_regs:
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.asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
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/* Registers common to both GICv2 and GICv3 */
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200-0x278)\nOffset\t\t\tValue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t 0x"
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prefix:
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.asciz "0x"
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/* ---------------------------------------------
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* The below utility macro prints out relevant GIC
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* registers whenever an unhandled exception is
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* taken in BL31 on ARM standard platforms.
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* Expects: GICD base in x16, GICC base in x17
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* Clobbers: x0 - x10, sp
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* ---------------------------------------------
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*/
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.macro arm_print_gic_regs
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/* Check for GICv3 system register access */
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mrs x7, id_aa64pfr0_el1
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ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x7, #1
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b.ne print_gicv2
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/* Check for SRE enable */
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mrs x8, ICC_SRE_EL3
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tst x8, #ICC_SRE_SRE_BIT
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b.eq print_gicv2
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/* Load the icc reg list to x6 */
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adr x6, icc_regs
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/* Load the icc regs to gp regs used by str_in_crash_buf_print */
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mrs x8, ICC_HPPIR0_EL1
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mrs x9, ICC_HPPIR1_EL1
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mrs x10, ICC_CTLR_EL3
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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b print_gic_common
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print_gicv2:
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/* Load the gicc reg list to x6 */
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adr x6, gicc_regs
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/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x17, #GICC_HPPIR]
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ldr w9, [x17, #GICC_AHPPIR]
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ldr w10, [x17, #GICC_CTLR]
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/* Store to the crash buf and print to console */
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bl str_in_crash_buf_print
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print_gic_common:
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/* Print the GICD_ISPENDR regs */
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add x7, x16, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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gicd_ispendr_loop:
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sub x4, x7, x16
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cmp x4, #0x280
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b.eq exit_print_gic_regs
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/* Print "0x" */
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adr x4, prefix
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bl asm_print_str
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/* Print offset */
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sub x4, x7, x16
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mov x5, #12
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bl asm_print_hex_bits
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b gicd_ispendr_loop
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exit_print_gic_regs:
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.endm
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#endif /* ARM_MACROS_S */
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