264 lines
6.6 KiB
C
264 lines
6.6 KiB
C
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <lib/el3_runtime/pubsub_events.h>
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#include <lib/extensions/amu.h>
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#include <lib/extensions/amu_private.h>
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#include <plat/common/platform.h>
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static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
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/*
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* Get AMU version value from pfr0.
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* Return values
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* ID_PFR0_AMU_V1: FEAT_AMUv1 supported (introduced in ARM v8.4)
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* ID_PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6)
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* ID_PFR0_AMU_NOT_SUPPORTED: not supported
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*/
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unsigned int amu_get_version(void)
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{
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return (unsigned int)(read_id_pfr0() >> ID_PFR0_AMU_SHIFT) &
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ID_PFR0_AMU_MASK;
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Check if group 1 counters is implemented */
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bool amu_group1_supported(void)
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{
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uint32_t features = read_amcfgr() >> AMCFGR_NCG_SHIFT;
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return (features & AMCFGR_NCG_MASK) == 1U;
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}
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#endif
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/*
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* Enable counters. This function is meant to be invoked
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* by the context management library before exiting from EL3.
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*/
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void amu_enable(bool el2_unused)
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{
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if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
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return;
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Check and set presence of group 1 counters */
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if (!amu_group1_supported()) {
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ERROR("AMU Counter Group 1 is not implemented\n");
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panic();
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}
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/* Check number of group 1 counters */
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uint32_t cnt_num = (read_amcgcr() >> AMCGCR_CG1NC_SHIFT) &
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AMCGCR_CG1NC_MASK;
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VERBOSE("%s%u. %s%u\n",
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"Number of AMU Group 1 Counters ", cnt_num,
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"Requested number ", AMU_GROUP1_NR_COUNTERS);
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if (cnt_num < AMU_GROUP1_NR_COUNTERS) {
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ERROR("%s%u is less than %s%u\n",
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"Number of AMU Group 1 Counters ", cnt_num,
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"Requested number ", AMU_GROUP1_NR_COUNTERS);
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panic();
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}
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#endif
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if (el2_unused) {
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uint64_t v;
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/*
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* Non-secure access from EL0 or EL1 to the Activity Monitor
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* registers do not trap to EL2.
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*/
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v = read_hcptr();
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v &= ~TAM_BIT;
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write_hcptr(v);
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}
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/* Enable group 0 counters */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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#if AMU_GROUP1_NR_COUNTERS
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/* Enable group 1 counters */
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write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
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#endif
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/* Initialize FEAT_AMUv1p1 features if present. */
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if (amu_get_version() < ID_PFR0_AMU_V1P1) {
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return;
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}
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#if AMU_RESTRICT_COUNTERS
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/*
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* FEAT_AMUv1p1 adds a register field to restrict access to group 1
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* counters at all but the highest implemented EL. This is controlled
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* with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
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* register reads at lower ELs return zero. Reads from the memory
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* mapped view are unaffected.
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*/
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VERBOSE("AMU group 1 counter access restricted.\n");
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write_amcr(read_amcr() | AMCR_CG1RZ_BIT);
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#else
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write_amcr(read_amcr() & ~AMCR_CG1RZ_BIT);
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#endif
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}
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/* Read the group 0 counter identified by the given `idx`. */
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uint64_t amu_group0_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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return amu_group0_cnt_read_internal(idx);
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}
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/* Write the group 0 counter identified by the given `idx` with `val` */
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void amu_group0_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(idx < AMU_GROUP0_NR_COUNTERS);
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amu_group0_cnt_write_internal(idx, val);
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isb();
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Read the group 1 counter identified by the given `idx` */
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uint64_t amu_group1_cnt_read(unsigned int idx)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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return amu_group1_cnt_read_internal(idx);
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}
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/* Write the group 1 counter identified by the given `idx` with `val` */
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void amu_group1_cnt_write(unsigned int idx, uint64_t val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_cnt_write_internal(idx, val);
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isb();
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}
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/*
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* Program the event type register for the given `idx` with
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* the event number `val`
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*/
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void amu_group1_set_evtype(unsigned int idx, unsigned int val)
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{
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assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
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assert(amu_group1_supported());
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assert(idx < AMU_GROUP1_NR_COUNTERS);
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amu_group1_set_evtype_internal(idx, val);
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isb();
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}
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#endif /* AMU_GROUP1_NR_COUNTERS */
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static void *amu_context_save(const void *arg)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int i;
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if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
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return (void *)-1;
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}
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#if AMU_GROUP1_NR_COUNTERS
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if (!amu_group1_supported()) {
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return (void *)-1;
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}
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#endif
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/* Assert that group 0/1 counter configuration is what we expect */
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assert(read_amcntenset0_el0() == AMU_GROUP0_COUNTERS_MASK);
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#if AMU_GROUP1_NR_COUNTERS
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assert(read_amcntenset1_el0() == AMU_GROUP1_COUNTERS_MASK);
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#endif
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/*
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* Disable group 0/1 counters to avoid other observers like SCP sampling
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* counter values from the future via the memory mapped view.
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*/
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write_amcntenclr0(AMU_GROUP0_COUNTERS_MASK);
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#if AMU_GROUP1_NR_COUNTERS
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write_amcntenclr1(AMU_GROUP1_COUNTERS_MASK);
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#endif
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isb();
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/* Save all group 0 counters */
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for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
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ctx->group0_cnts[i] = amu_group0_cnt_read(i);
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}
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#if AMU_GROUP1_NR_COUNTERS
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/* Save group 1 counters */
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for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
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if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
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ctx->group1_cnts[i] = amu_group1_cnt_read(i);
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}
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}
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#endif
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return (void *)0;
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}
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static void *amu_context_restore(const void *arg)
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{
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struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
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unsigned int i;
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if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
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return (void *)-1;
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}
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#if AMU_GROUP1_NR_COUNTERS
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if (!amu_group1_supported()) {
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return (void *)-1;
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}
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#endif
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/* Counters were disabled in `amu_context_save()` */
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assert(read_amcntenset0_el0() == 0U);
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#if AMU_GROUP1_NR_COUNTERS
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assert(read_amcntenset1_el0() == 0U);
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#endif
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/* Restore all group 0 counters */
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for (i = 0U; i < AMU_GROUP0_NR_COUNTERS; i++) {
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amu_group0_cnt_write(i, ctx->group0_cnts[i]);
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}
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/* Restore group 0 counter configuration */
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write_amcntenset0(AMU_GROUP0_COUNTERS_MASK);
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#if AMU_GROUP1_NR_COUNTERS
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/* Restore group 1 counters */
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for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
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if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
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amu_group1_cnt_write(i, ctx->group1_cnts[i]);
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}
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}
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/* Restore group 1 counter configuration */
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write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
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#endif
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return (void *)0;
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}
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_start, amu_context_save);
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SUBSCRIBE_TO_EVENT(psci_suspend_pwrdown_finish, amu_context_restore);
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