386 lines
10 KiB
ArmAsm
386 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <assert_macros.S>
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#include <asm_macros.S>
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.globl amu_group0_cnt_read_internal
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.globl amu_group0_cnt_write_internal
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.globl amu_group1_cnt_read_internal
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.globl amu_group1_cnt_write_internal
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.globl amu_group1_set_evtype_internal
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/* FEAT_AMUv1p1 virtualisation offset register functions */
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.globl amu_group0_voffset_read_internal
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.globl amu_group0_voffset_write_internal
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.globl amu_group1_voffset_read_internal
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.globl amu_group1_voffset_write_internal
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/*
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* uint64_t amu_group0_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `x0`.
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*/
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func amu_group0_cnt_read_internal
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adr x1, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~3
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x1, x1, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x1
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1: read AMEVCNTR00_EL0 /* index 0 */
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read AMEVCNTR01_EL0 /* index 1 */
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read AMEVCNTR02_EL0 /* index 2 */
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read AMEVCNTR03_EL0 /* index 3 */
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endfunc amu_group0_cnt_read_internal
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/*
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* void amu_group0_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func amu_group0_cnt_write_internal
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adr x2, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~3
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write AMEVCNTR00_EL0 /* index 0 */
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write AMEVCNTR01_EL0 /* index 1 */
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write AMEVCNTR02_EL0 /* index 2 */
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write AMEVCNTR03_EL0 /* index 3 */
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endfunc amu_group0_cnt_write_internal
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/*
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* uint64_t amu_group1_cnt_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU counter
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* and return it in `x0`.
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*/
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func amu_group1_cnt_read_internal
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adr x1, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~0xF
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x1, x1, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x1
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1: read AMEVCNTR10_EL0 /* index 0 */
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read AMEVCNTR11_EL0 /* index 1 */
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read AMEVCNTR12_EL0 /* index 2 */
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read AMEVCNTR13_EL0 /* index 3 */
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read AMEVCNTR14_EL0 /* index 4 */
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read AMEVCNTR15_EL0 /* index 5 */
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read AMEVCNTR16_EL0 /* index 6 */
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read AMEVCNTR17_EL0 /* index 7 */
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read AMEVCNTR18_EL0 /* index 8 */
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read AMEVCNTR19_EL0 /* index 9 */
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read AMEVCNTR1A_EL0 /* index 10 */
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read AMEVCNTR1B_EL0 /* index 11 */
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read AMEVCNTR1C_EL0 /* index 12 */
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read AMEVCNTR1D_EL0 /* index 13 */
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read AMEVCNTR1E_EL0 /* index 14 */
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read AMEVCNTR1F_EL0 /* index 15 */
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endfunc amu_group1_cnt_read_internal
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/*
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* void amu_group1_cnt_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU counter.
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*/
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func amu_group1_cnt_write_internal
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adr x2, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~0xF
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write AMEVCNTR10_EL0 /* index 0 */
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write AMEVCNTR11_EL0 /* index 1 */
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write AMEVCNTR12_EL0 /* index 2 */
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write AMEVCNTR13_EL0 /* index 3 */
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write AMEVCNTR14_EL0 /* index 4 */
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write AMEVCNTR15_EL0 /* index 5 */
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write AMEVCNTR16_EL0 /* index 6 */
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write AMEVCNTR17_EL0 /* index 7 */
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write AMEVCNTR18_EL0 /* index 8 */
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write AMEVCNTR19_EL0 /* index 9 */
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write AMEVCNTR1A_EL0 /* index 10 */
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write AMEVCNTR1B_EL0 /* index 11 */
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write AMEVCNTR1C_EL0 /* index 12 */
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write AMEVCNTR1D_EL0 /* index 13 */
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write AMEVCNTR1E_EL0 /* index 14 */
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write AMEVCNTR1F_EL0 /* index 15 */
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endfunc amu_group1_cnt_write_internal
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/*
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* void amu_group1_set_evtype_internal(int idx, unsigned int val);
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*
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* Program the AMU event type register indexed by `idx`
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* with the value `val`.
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*/
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func amu_group1_set_evtype_internal
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adr x2, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~0xF
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ASM_ASSERT(eq)
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/* val should be between [0, 65535] */
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tst x1, #~0xFFFF
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of msr/ret instruction pair
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* in the table below.
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*/
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write AMEVTYPER10_EL0 /* index 0 */
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write AMEVTYPER11_EL0 /* index 1 */
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write AMEVTYPER12_EL0 /* index 2 */
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write AMEVTYPER13_EL0 /* index 3 */
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write AMEVTYPER14_EL0 /* index 4 */
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write AMEVTYPER15_EL0 /* index 5 */
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write AMEVTYPER16_EL0 /* index 6 */
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write AMEVTYPER17_EL0 /* index 7 */
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write AMEVTYPER18_EL0 /* index 8 */
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write AMEVTYPER19_EL0 /* index 9 */
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write AMEVTYPER1A_EL0 /* index 10 */
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write AMEVTYPER1B_EL0 /* index 11 */
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write AMEVTYPER1C_EL0 /* index 12 */
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write AMEVTYPER1D_EL0 /* index 13 */
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write AMEVTYPER1E_EL0 /* index 14 */
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write AMEVTYPER1F_EL0 /* index 15 */
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endfunc amu_group1_set_evtype_internal
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/*
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* Accessor functions for virtual offset registers added with FEAT_AMUv1p1
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*/
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/*
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* uint64_t amu_group0_voffset_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU virtual offset register
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* and return it in `x0`.
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*/
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func amu_group0_voffset_read_internal
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adr x1, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~3
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ASM_ASSERT(eq)
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/* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */
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cmp x0, #1
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ASM_ASSERT(ne)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x1, x1, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x1
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1: read AMEVCNTVOFF00_EL2 /* index 0 */
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.skip 8 /* AMEVCNTVOFF01_EL2 does not exist */
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#if ENABLE_BTI
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.skip 4
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#endif
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read AMEVCNTVOFF02_EL2 /* index 2 */
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read AMEVCNTVOFF03_EL2 /* index 3 */
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endfunc amu_group0_voffset_read_internal
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/*
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* void amu_group0_voffset_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU virtual offset register.
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*/
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func amu_group0_voffset_write_internal
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adr x2, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~3
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ASM_ASSERT(eq)
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/* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */
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cmp x0, #1
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ASM_ASSERT(ne)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write AMEVCNTVOFF00_EL2 /* index 0 */
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.skip 8 /* AMEVCNTVOFF01_EL2 does not exist */
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#if ENABLE_BTI
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.skip 4
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#endif
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write AMEVCNTVOFF02_EL2 /* index 2 */
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write AMEVCNTVOFF03_EL2 /* index 3 */
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endfunc amu_group0_voffset_write_internal
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/*
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* uint64_t amu_group1_voffset_read_internal(int idx);
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*
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* Given `idx`, read the corresponding AMU virtual offset register
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* and return it in `x0`.
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*/
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func amu_group1_voffset_read_internal
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adr x1, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~0xF
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x1, x1, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x1
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1: read AMEVCNTVOFF10_EL2 /* index 0 */
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read AMEVCNTVOFF11_EL2 /* index 1 */
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read AMEVCNTVOFF12_EL2 /* index 2 */
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read AMEVCNTVOFF13_EL2 /* index 3 */
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read AMEVCNTVOFF14_EL2 /* index 4 */
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read AMEVCNTVOFF15_EL2 /* index 5 */
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read AMEVCNTVOFF16_EL2 /* index 6 */
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read AMEVCNTVOFF17_EL2 /* index 7 */
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read AMEVCNTVOFF18_EL2 /* index 8 */
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read AMEVCNTVOFF19_EL2 /* index 9 */
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read AMEVCNTVOFF1A_EL2 /* index 10 */
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read AMEVCNTVOFF1B_EL2 /* index 11 */
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read AMEVCNTVOFF1C_EL2 /* index 12 */
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read AMEVCNTVOFF1D_EL2 /* index 13 */
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read AMEVCNTVOFF1E_EL2 /* index 14 */
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read AMEVCNTVOFF1F_EL2 /* index 15 */
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endfunc amu_group1_voffset_read_internal
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/*
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* void amu_group1_voffset_write_internal(int idx, uint64_t val);
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*
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* Given `idx`, write `val` to the corresponding AMU virtual offset register.
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*/
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func amu_group1_voffset_write_internal
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adr x2, 1f
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#if ENABLE_ASSERTIONS
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/*
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* It can be dangerous to call this function with an
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* out of bounds index. Ensure `idx` is valid.
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*/
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tst x0, #~0xF
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ASM_ASSERT(eq)
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#endif
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/*
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* Given `idx` calculate address of mrs/ret instruction pair
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* in the table below.
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*/
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add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
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#if ENABLE_BTI
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add x2, x2, x0, lsl #2 /* + "bti j" instruction */
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#endif
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br x2
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1: write AMEVCNTVOFF10_EL2 /* index 0 */
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write AMEVCNTVOFF11_EL2 /* index 1 */
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write AMEVCNTVOFF12_EL2 /* index 2 */
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write AMEVCNTVOFF13_EL2 /* index 3 */
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write AMEVCNTVOFF14_EL2 /* index 4 */
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write AMEVCNTVOFF15_EL2 /* index 5 */
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write AMEVCNTVOFF16_EL2 /* index 6 */
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write AMEVCNTVOFF17_EL2 /* index 7 */
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write AMEVCNTVOFF18_EL2 /* index 8 */
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write AMEVCNTVOFF19_EL2 /* index 9 */
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write AMEVCNTVOFF1A_EL2 /* index 10 */
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write AMEVCNTVOFF1B_EL2 /* index 11 */
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write AMEVCNTVOFF1C_EL2 /* index 12 */
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write AMEVCNTVOFF1D_EL2 /* index 13 */
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write AMEVCNTVOFF1E_EL2 /* index 14 */
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write AMEVCNTVOFF1F_EL2 /* index 15 */
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endfunc amu_group1_voffset_write_internal
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