260 lines
6.8 KiB
C
260 lines
6.8 KiB
C
/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/allwinner/axp.h>
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <lib/mmio.h>
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#include <core_off_arisc.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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static enum pmic_type {
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UNKNOWN,
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GENERIC_H5,
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GENERIC_A64,
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REF_DESIGN_H5, /* regulators controlled by GPIO pins on port L */
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AXP803_RSB, /* PMIC connected via RSB on most A64 boards */
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} pmic;
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#define AXP803_HW_ADDR 0x3a3
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#define AXP803_RT_ADDR 0x2d
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/*
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* On boards without a proper PMIC we struggle to turn off the system properly.
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* Try to turn off as much off the system as we can, to reduce power
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* consumption. This should be entered with only one core running and SMP
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* disabled.
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* This function only cares about peripherals.
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*/
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static void sunxi_turn_off_soc(uint16_t socid)
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{
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int i;
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/** Turn off most peripherals, most importantly DRAM users. **/
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/* Keep DRAM controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, ~BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, ~BIT_32(14));
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/* Contains msgbox (bit 21) and spinlock (bit 22) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2c4, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x64, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x2c8, 0);
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/* Keep PIO controller running for now. */
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x68, ~(BIT_32(5)));
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mmio_write_32(SUNXI_CCU_BASE + 0x2d0, 0);
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/* Contains UART0 (bit 16) */
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mmio_write_32(SUNXI_CCU_BASE + 0x2d8, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x6c, 0);
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mmio_write_32(SUNXI_CCU_BASE + 0x70, 0);
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/** Turn off DRAM controller. **/
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c0, BIT_32(14));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x60, BIT_32(14));
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/** Migrate CPU and bus clocks away from the PLLs. **/
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/* AHB1: use OSC24M/1, APB1 = AHB1 / 2 */
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mmio_write_32(SUNXI_CCU_BASE + 0x54, 0x1000);
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/* APB2: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x58, 0x1000000);
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/* AHB2: use AHB1 clock */
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mmio_write_32(SUNXI_CCU_BASE + 0x5c, 0);
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/* CPU: use OSC24M */
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mmio_write_32(SUNXI_CCU_BASE + 0x50, 0x10000);
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/** Turn off PLLs. **/
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for (i = 0; i < 6; i++)
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mmio_clrbits_32(SUNXI_CCU_BASE + i * 8, BIT(31));
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switch (socid) {
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case SUNXI_SOC_H5:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x44, BIT(31));
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break;
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case SUNXI_SOC_A64:
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x2c, BIT(31));
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mmio_clrbits_32(SUNXI_CCU_BASE + 0x4c, BIT(31));
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break;
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}
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}
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static int rsb_init(void)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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return ret;
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/* Switch to the recommended 3 MHz bus clock. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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return ret;
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/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
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ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
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if (ret)
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return ret;
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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ret = rsb_assign_runtime_address(AXP803_HW_ADDR,
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AXP803_RT_ADDR);
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if (ret)
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return ret;
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return axp_check_id();
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}
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int axp_read(uint8_t reg)
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{
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return rsb_read(AXP803_RT_ADDR, reg);
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}
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int axp_write(uint8_t reg, uint8_t val)
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{
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return rsb_write(AXP803_RT_ADDR, reg, val);
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}
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int sunxi_pmic_setup(uint16_t socid, const void *fdt)
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{
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int ret;
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switch (socid) {
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case SUNXI_SOC_H5:
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NOTICE("PMIC: Assuming H5 reference regulator design\n");
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pmic = REF_DESIGN_H5;
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break;
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case SUNXI_SOC_A64:
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pmic = GENERIC_A64;
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INFO("PMIC: Probing AXP803 on RSB\n");
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ret = sunxi_init_platform_r_twi(socid, true);
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if (ret)
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return ret;
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ret = rsb_init();
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if (ret)
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return ret;
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pmic = AXP803_RSB;
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axp_setup_regulators(fdt);
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/* Switch the PMIC back to I2C mode. */
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ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
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if (ret)
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return ret;
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break;
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default:
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return -ENODEV;
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}
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return 0;
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}
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void sunxi_power_down(void)
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{
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switch (pmic) {
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case GENERIC_H5:
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/* Turn off as many peripherals and clocks as we can. */
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sunxi_turn_off_soc(SUNXI_SOC_H5);
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/* Turn off the pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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break;
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case GENERIC_A64:
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/* Turn off as many peripherals and clocks as we can. */
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sunxi_turn_off_soc(SUNXI_SOC_A64);
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/* Turn off the pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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break;
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case REF_DESIGN_H5:
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sunxi_turn_off_soc(SUNXI_SOC_H5);
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/*
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* Switch PL pins to power off the board:
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* - PL5 (VCC_IO) -> high
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* - PL8 (PWR-STB = CPU power supply) -> low
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* - PL9 (PWR-DRAM) ->low
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* - PL10 (power LED) -> low
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* Note: Clearing PL8 will reset the board, so keep it up.
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*/
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sunxi_set_gpio_out('L', 5, 1);
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sunxi_set_gpio_out('L', 9, 0);
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sunxi_set_gpio_out('L', 10, 0);
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/* Turn off pin controller now. */
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mmio_write_32(SUNXI_CCU_BASE + 0x68, 0);
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break;
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case AXP803_RSB:
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/* (Re-)init RSB in case the rich OS has disabled it. */
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sunxi_init_platform_r_twi(SUNXI_SOC_A64, true);
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rsb_init();
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axp_power_off();
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break;
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default:
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break;
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}
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}
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/* This lock synchronises access to the arisc management processor. */
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static DEFINE_BAKERY_LOCK(arisc_lock);
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/*
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* If we are supposed to turn ourself off, tell the arisc SCP to do that
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* work for us. Without any SCPI provider running there, we place some
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* OpenRISC code into SRAM, put the address of that into the reset vector
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* and release the arisc reset line. The SCP will wait for the core to enter
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* WFI, then execute that code and pull the line up again.
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* The code expects the core mask to be patched into the first instruction.
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*/
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void sunxi_cpu_power_off_self(void)
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{
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u_register_t mpidr = read_mpidr();
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
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uint32_t *code = arisc_core_off;
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do {
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bakery_lock_get(&arisc_lock);
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/* Wait until the arisc is in reset state. */
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if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
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break;
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bakery_lock_release(&arisc_lock);
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} while (1);
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/* Patch up the code to feed in an input parameter. */
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code[0] = (code[0] & ~0xffff) | BIT_32(core);
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clean_dcache_range((uintptr_t)code, sizeof(arisc_core_off));
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/*
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* The OpenRISC unconditional branch has opcode 0, the branch offset
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* is in the lower 26 bits, containing the distance to the target,
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* in instruction granularity (32 bits).
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*/
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mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
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/* De-assert the arisc reset line to let it run. */
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mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
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/*
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* We release the lock here, although the arisc is still busy.
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* But as long as it runs, the reset line is high, so other users
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* won't leave the loop above.
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* Once it has finished, the code is supposed to clear the reset line,
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* to signal this to other users.
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*/
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bakery_lock_release(&arisc_lock);
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}
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