122 lines
2.4 KiB
C
122 lines
2.4 KiB
C
/*
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* Copyright (c) 2017-2020, ARM Limited. All rights reserved.
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* Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <string.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/allwinner/axp.h>
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#include <drivers/allwinner/sunxi_rsb.h>
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#include <lib/mmio.h>
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#include <sunxi_cpucfg.h>
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#include <sunxi_def.h>
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#include <sunxi_mmap.h>
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#include <sunxi_private.h>
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#define AXP305_I2C_ADDR 0x36
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#define AXP305_HW_ADDR 0x745
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#define AXP305_RT_ADDR 0x3a
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static enum pmic_type {
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UNKNOWN,
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AXP305,
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} pmic;
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int axp_read(uint8_t reg)
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{
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return rsb_read(AXP305_RT_ADDR, reg);
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}
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int axp_write(uint8_t reg, uint8_t val)
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{
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return rsb_write(AXP305_RT_ADDR, reg, val);
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}
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static int rsb_init(void)
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{
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int ret;
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ret = rsb_init_controller();
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if (ret)
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return ret;
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/* Switch to the recommended 3 MHz bus clock. */
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ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
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if (ret)
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return ret;
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/* Initiate an I2C transaction to switch the PMIC to RSB mode. */
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ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
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if (ret)
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return ret;
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/* Associate the 8-bit runtime address with the 12-bit bus address. */
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ret = rsb_assign_runtime_address(AXP305_HW_ADDR, AXP305_RT_ADDR);
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if (ret)
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return ret;
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return axp_check_id();
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}
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int sunxi_pmic_setup(uint16_t socid, const void *fdt)
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{
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int ret;
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INFO("PMIC: Probing AXP305 on RSB\n");
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ret = sunxi_init_platform_r_twi(socid, true);
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if (ret) {
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INFO("Could not init platform bus: %d\n", ret);
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return ret;
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}
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ret = rsb_init();
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if (ret) {
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INFO("Could not init RSB: %d\n", ret);
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return ret;
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}
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pmic = AXP305;
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axp_setup_regulators(fdt);
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/* Switch the PMIC back to I2C mode. */
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ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
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if (ret)
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return ret;
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return 0;
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}
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void sunxi_power_down(void)
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{
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switch (pmic) {
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case AXP305:
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/* Re-initialise after rich OS might have used it. */
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sunxi_init_platform_r_twi(SUNXI_SOC_H616, true);
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rsb_init();
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axp_power_off();
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break;
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default:
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break;
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}
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}
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void sunxi_cpu_power_off_self(void)
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{
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u_register_t mpidr = read_mpidr();
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unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
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/* Enable the CPUIDLE hardware (only really needs to be done once). */
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mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
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mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
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/* Trigger power off for this core. */
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mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
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}
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