147 lines
3.9 KiB
C
147 lines
3.9 KiB
C
/*
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* Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <bl1/bl1.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/smmu_v3.h>
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#include <drivers/arm/sp805.h>
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#include <lib/mmio.h>
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/common/platform.h>
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#include "fvp_private.h"
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in Interconnect for the primary CPU's cluster.
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*/
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fvp_interconnect_enable();
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}
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void plat_arm_secure_wdt_start(void)
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{
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sp805_stop(ARM_SP805_TWDG_BASE);
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}
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void bl1_platform_setup(void)
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{
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arm_bl1_platform_setup();
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/* Initialize System level generic or SP804 timer */
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fvp_timer_init();
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/* On FVP RevC, initialize SMMUv3 */
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if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U)
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smmuv3_security_init(PLAT_FVP_SMMUV3_BASE);
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}
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__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
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{
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uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
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/* Clear the NV flags register. */
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mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
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nv_flags);
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/* Setup the watchdog to reset the system as soon as possible */
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sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
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while (true)
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wfi();
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}
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#if MEASURED_BOOT
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/*
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* Calculates and writes BL2 hash data to TB_FW_CONFIG DTB.
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*/
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void bl1_plat_set_bl2_hash(const image_desc_t *image_desc)
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{
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arm_bl1_set_bl2_hash(image_desc);
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}
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/*
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* Implementation for bl1_plat_handle_post_image_load(). This function
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* populates the default arguments to BL2. The BL2 memory layout structure
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* is allocated and the calculated layout is populated in arg1 to BL2.
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*/
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int bl1_plat_handle_post_image_load(unsigned int image_id)
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{
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meminfo_t *bl2_tzram_layout;
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meminfo_t *bl1_tzram_layout;
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image_desc_t *image_desc;
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entry_point_info_t *ep_info;
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if (image_id != BL2_IMAGE_ID) {
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return 0;
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}
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/* Get the image descriptor */
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image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(image_desc != NULL);
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/* Calculate BL2 hash and set it in TB_FW_CONFIG */
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bl1_plat_set_bl2_hash(image_desc);
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/* Get the entry point info */
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ep_info = &image_desc->ep_info;
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/* Find out how much free trusted ram remains after BL1 load */
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bl1_tzram_layout = bl1_plat_sec_mem_layout();
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/*
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* Create a new layout of memory for BL2 as seen by BL1 i.e.
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* tell it the amount of total and free memory available.
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* This layout is created at the first free address visible
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* to BL2. BL2 will read the memory layout before using its
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* memory for other purposes.
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*/
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bl2_tzram_layout = (meminfo_t *)bl1_tzram_layout->total_base;
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bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
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ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
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VERBOSE("BL1: BL2 memory layout address = %p\n",
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(void *)bl2_tzram_layout);
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return 0;
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}
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#endif /* MEASURED_BOOT */
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/*******************************************************************************
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* The following function checks if Firmware update is needed by checking error
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* reported in NV flag.
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******************************************************************************/
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bool plat_arm_bl1_fwu_needed(void)
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{
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int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
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/* if image load/authentication failed */
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return ((nv_flags == -EAUTH) || (nv_flags == -ENOENT));
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}
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