276 lines
8.9 KiB
ArmAsm
276 lines
8.9 KiB
ArmAsm
/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a53.h>
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#include <cortex_a57.h>
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#include <cortex_a72.h>
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#include <cpu_macros.S>
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#include <platform_def.h>
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.globl plat_reset_handler
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.globl plat_arm_calc_core_pos
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#if JUNO_AARCH32_EL3_RUNTIME
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.globl plat_get_my_entrypoint
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.globl juno_reset_to_aarch32_state
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#endif
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#define JUNO_REVISION(rev) REV_JUNO_R##rev
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#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev
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#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \
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jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision)
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/* --------------------------------------------------------------------
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* Helper macro to jump to the given handler if the board revision
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* matches.
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* Expects the Juno board revision in x0.
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* --------------------------------------------------------------------
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*/
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.macro jump_to_handler _revision, _handler
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cmp x0, #\_revision
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b.eq \_handler
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.endm
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R0.
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*
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* Juno R0 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A57 processor cluster.
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*
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* This handler does the following:
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* - Implement workaround for defect id 831273 by enabling an event
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* stream every 65536 cycles.
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(0)
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/* --------------------------------------------------------------------
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* Enable the event stream every 65536 cycles
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* --------------------------------------------------------------------
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*/
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mov x0, #(0xf << EVNTI_SHIFT)
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orr x0, x0, #EVNTEN_BIT
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msr CNTKCTL_EL1, x0
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/* --------------------------------------------------------------------
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* Nothing else to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A53_MIDR, 1f
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT))
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msr CORTEX_A57_L2CTLR_EL1, x0
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1:
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isb
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ret
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endfunc JUNO_HANDLER(0)
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R1.
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*
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* Juno R1 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A57 processor cluster.
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*
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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*
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* Note that:
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* - The default value for the L2 Tag RAM latency for Cortex-A57 is
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* suitable.
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* - Defect #831273 doesn't affect Juno R1.
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(1)
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/* --------------------------------------------------------------------
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* Nothing to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A57_MIDR, A57
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ret
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A57:
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT)
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msr CORTEX_A57_L2CTLR_EL1, x0
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isb
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ret
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endfunc JUNO_HANDLER(1)
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/* --------------------------------------------------------------------
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* Platform reset handler for Juno R2.
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*
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* Juno R2 has the following topology:
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* - Quad core Cortex-A53 processor cluster;
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* - Dual core Cortex-A72 processor cluster.
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*
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* This handler does the following:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72
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* - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72
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*
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* Note that:
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* - Defect #831273 doesn't affect Juno R2.
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* --------------------------------------------------------------------
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*/
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func JUNO_HANDLER(2)
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/* --------------------------------------------------------------------
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* Nothing to do on Cortex-A53.
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* --------------------------------------------------------------------
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*/
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jump_if_cpu_midr CORTEX_A72_MIDR, A72
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ret
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A72:
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/* --------------------------------------------------------------------
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* Cortex-A72 specific settings
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* --------------------------------------------------------------------
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*/
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mov x0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \
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(CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT))
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msr CORTEX_A57_L2CTLR_EL1, x0
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isb
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ret
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endfunc JUNO_HANDLER(2)
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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*
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* Determine the Juno board revision and call the appropriate reset
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* handler.
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* --------------------------------------------------------------------
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*/
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func plat_reset_handler
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/* Read the V2M SYS_ID register */
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mov_imm x0, (V2M_SYSREGS_BASE + V2M_SYS_ID)
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ldr w1, [x0]
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/* Extract board revision from the SYS_ID */
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ubfx x0, x1, #V2M_SYS_ID_REV_SHIFT, #4
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JUMP_TO_HANDLER_IF_JUNO_R(0)
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JUMP_TO_HANDLER_IF_JUNO_R(1)
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JUMP_TO_HANDLER_IF_JUNO_R(2)
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/* Board revision is not supported */
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no_ret plat_panic_handler
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endfunc plat_reset_handler
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/* -----------------------------------------------------
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* void juno_do_reset_to_aarch32_state(void);
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*
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* Request warm reset to AArch32 mode.
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* -----------------------------------------------------
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*/
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func juno_do_reset_to_aarch32_state
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mov x0, #RMR_EL3_RR_BIT
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dsb sy
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msr rmr_el3, x0
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isb
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wfi
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b plat_panic_handler
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endfunc juno_do_reset_to_aarch32_state
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/* -----------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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* Helper function to calculate the core position.
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* -----------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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b css_calc_core_pos_swap_cluster
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endfunc plat_arm_calc_core_pos
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#if JUNO_AARCH32_EL3_RUNTIME
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot. On JUNO platform, this distinction is based on the contents of
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* the Trusted Mailbox. It is initialised to zero by the SCP before the
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* AP cores are released from reset. Therefore, a zero mailbox means
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* it's a cold reset. If it is a warm boot then a request to reset to
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* AArch32 state is issued. This is the only way to reset to AArch32
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* in EL3 on Juno. A trampoline located at the high vector address
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* has already been prepared by BL1.
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*
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* This functions returns the contents of the mailbox, i.e.:
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* - 0 for a cold boot;
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* - request warm reset in AArch32 state for warm boot case;
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov_imm x0, PLAT_ARM_TRUSTED_MAILBOX_BASE
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ldr x0, [x0]
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cbz x0, return
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b juno_do_reset_to_aarch32_state
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return:
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ret
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endfunc plat_get_my_entrypoint
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/*
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* Emit a "movw r0, #imm16" which moves the lower
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* 16 bits of `_val` into r0.
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*/
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.macro emit_movw _reg_d, _val
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mov_imm \_reg_d, (0xe3000000 | \
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((\_val & 0xfff) | \
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((\_val & 0xf000) << 4)))
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.endm
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/*
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* Emit a "movt r0, #imm16" which moves the upper
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* 16 bits of `_val` into r0.
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*/
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.macro emit_movt _reg_d, _val
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mov_imm \_reg_d, (0xe3400000 | \
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(((\_val & 0x0fff0000) >> 16) | \
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((\_val & 0xf0000000) >> 12)))
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.endm
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/*
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* This function writes the trampoline code at HI-VEC (0xFFFF0000)
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* address which loads r0 with the entrypoint address for
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* BL32 (a.k.a SP_MIN) when EL3 is in AArch32 mode. A warm reset
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* to AArch32 mode is then requested by writing into RMR_EL3.
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*/
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func juno_reset_to_aarch32_state
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/*
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* Invalidate all caches before the warm reset to AArch32 state.
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* This is required on the Juno AArch32 boot flow because the L2
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* unified cache may contain code and data from when the processor
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* was still executing in AArch64 state. This code only runs on
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* the primary core, all other cores are powered down.
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*/
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mov x0, #DCISW
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bl dcsw_op_all
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emit_movw w0, BL32_BASE
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emit_movt w1, BL32_BASE
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/* opcode "bx r0" to branch using r0 in AArch32 mode */
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mov_imm w2, 0xe12fff10
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/* Write the above opcodes at HI-VECTOR location */
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mov_imm x3, HI_VECTOR_BASE
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str w0, [x3], #4
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str w1, [x3], #4
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str w2, [x3]
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b juno_do_reset_to_aarch32_state
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endfunc juno_reset_to_aarch32_state
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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