123 lines
3.3 KiB
C
123 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/css/sds.h>
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#include <drivers/arm/sp805.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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void juno_reset_to_aarch32_state(void);
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static int is_watchdog_reset(void)
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{
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#if !CSS_USE_SCMI_SDS_DRIVER
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#define RESET_REASON_WDOG_RESET (0x2)
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const uint32_t *reset_flags_ptr = (const uint32_t *)SSC_GPRETN;
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if ((*reset_flags_ptr & RESET_REASON_WDOG_RESET) != 0)
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return 1;
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return 0;
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#else
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int ret;
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uint32_t scp_reset_synd_flags;
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ret = sds_init();
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if (ret != SDS_OK) {
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ERROR("SCP SDS initialization failed\n");
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panic();
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}
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ret = sds_struct_read(SDS_RESET_SYNDROME_STRUCT_ID,
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SDS_RESET_SYNDROME_OFFSET,
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&scp_reset_synd_flags,
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SDS_RESET_SYNDROME_SIZE,
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SDS_ACCESS_MODE_NON_CACHED);
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if (ret != SDS_OK) {
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ERROR("Getting reset reason from SDS failed\n");
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panic();
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}
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/* Check if the WATCHDOG_RESET_BIT is set in the reset syndrome */
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if (scp_reset_synd_flags & SDS_RESET_SYNDROME_AP_WD_RESET_BIT)
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return 1;
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return 0;
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#endif
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}
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/*******************************************************************************
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* The following function checks if Firmware update is needed,
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* by checking if TOC in FIP image is valid or watchdog reset happened.
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******************************************************************************/
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bool plat_arm_bl1_fwu_needed(void)
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{
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int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
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/* Check if TOC is invalid or watchdog reset happened. */
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return (!arm_io_is_toc_valid() || (((nv_flags == -EAUTH) ||
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(nv_flags == -ENOENT)) && is_watchdog_reset()));
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}
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/*******************************************************************************
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* On JUNO update the arg2 with address of SCP_BL2U image info.
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******************************************************************************/
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void bl1_plat_set_ep_info(unsigned int image_id,
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entry_point_info_t *ep_info)
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{
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if (image_id == BL2U_IMAGE_ID) {
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image_desc_t *image_desc = bl1_plat_get_image_desc(SCP_BL2U_IMAGE_ID);
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ep_info->args.arg2 = (unsigned long)&image_desc->image_info;
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}
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}
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/*******************************************************************************
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* On Juno clear SYS_NVFLAGS and wait for watchdog reset.
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******************************************************************************/
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__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
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{
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uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
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/* Clear the NV flags register. */
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mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
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nv_flags);
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/* Setup the watchdog to reset the system as soon as possible */
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sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
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while (true)
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wfi();
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}
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#if JUNO_AARCH32_EL3_RUNTIME
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Disable watchdog before leaving BL1 */
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sp805_stop(ARM_SP805_TWDG_BASE);
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#endif
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juno_reset_to_aarch32_state();
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}
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#endif /* JUNO_AARCH32_EL3_RUNTIME */
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void plat_arm_secure_wdt_start(void)
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{
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sp805_stop(ARM_SP805_TWDG_BASE);
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}
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