101 lines
2.7 KiB
C
101 lines
2.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SOC_TZASC_H
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#define SOC_TZASC_H
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#define MAX_NUM_TZC_REGION 3
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/* TZASC related constants */
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#define TZASC_CONFIGURATION_REG 0x000
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#define TZASC_SECURITY_INV_REG 0x034
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#define TZASC_SECURITY_INV_EN 0x1
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#define TZASC_REGIONS_REG 0x100
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/* As region address should address atleast 32KB memory. */
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#define TZASC_REGION_LOWADDR_MASK 0xFFFF8000
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#define TZASC_REGION_LOWADDR_OFFSET 0x0
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#define TZASC_REGION_HIGHADDR_OFFSET 0x4
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#define TZASC_REGION_ATTR_OFFSET 0x8
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#define TZASC_REGION_ENABLED 1
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#define TZASC_REGION_DISABLED 0
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#define TZASC_REGION_SIZE_32KB 0xE
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#define TZASC_REGION_SIZE_64KB 0xF
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#define TZASC_REGION_SIZE_128KB 0x10
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#define TZASC_REGION_SIZE_256KB 0x11
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#define TZASC_REGION_SIZE_512KB 0x12
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#define TZASC_REGION_SIZE_1MB 0x13
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#define TZASC_REGION_SIZE_2MB 0x14
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#define TZASC_REGION_SIZE_4MB 0x15
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#define TZASC_REGION_SIZE_8MB 0x16
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#define TZASC_REGION_SIZE_16MB 0x17
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#define TZASC_REGION_SIZE_32MB 0x18
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#define TZASC_REGION_SIZE_64MB 0x19
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#define TZASC_REGION_SIZE_128MB 0x1A
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#define TZASC_REGION_SIZE_256MB 0x1B
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#define TZASC_REGION_SIZE_512MB 0x1C
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#define TZASC_REGION_SIZE_1GB 0x1D
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#define TZASC_REGION_SIZE_2GB 0x1E
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#define TZASC_REGION_SIZE_4GB 0x1F
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#define TZASC_REGION_SIZE_8GB 0x20
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#define TZASC_REGION_SIZE_16GB 0x21
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#define TZASC_REGION_SIZE_32GB 0x22
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#define TZASC_REGION_SECURITY_SR (1 << 3)
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#define TZASC_REGION_SECURITY_SW (1 << 2)
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#define TZASC_REGION_SECURITY_SRW (TZASC_REGION_SECURITY_SR| \
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TZASC_REGION_SECURITY_SW)
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#define TZASC_REGION_SECURITY_NSR (1 << 1)
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#define TZASC_REGION_SECURITY_NSW 1
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#define TZASC_REGION_SECURITY_NSRW (TZASC_REGION_SECURITY_NSR| \
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TZASC_REGION_SECURITY_NSW)
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#define CSU_SEC_ACCESS_REG_OFFSET 0x21C
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#define TZASC_BYPASS_MUX_DISABLE 0x4
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#define CCI_TERMINATE_BARRIER_TX 0x8
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#define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000
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struct tzc380_reg {
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unsigned int secure;
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unsigned int enabled;
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unsigned int low_addr;
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unsigned int high_addr;
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unsigned int size;
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unsigned int sub_mask;
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};
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/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
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static const struct tzc380_reg tzc380_reg_list[] = {
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{
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TZASC_REGION_SECURITY_NSRW, /* .secure attr */
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0x0, /* .enabled */
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0x0, /* .lowaddr */
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0x0, /* .highaddr */
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0x0, /* .size */
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0x0, /* .submask */
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},
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{
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TZASC_REGION_SECURITY_SRW,
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TZASC_REGION_ENABLED,
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0xFC000000,
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0x0,
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TZASC_REGION_SIZE_64MB,
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0x80, /* Disable region 7 */
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},
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/* reserve 2M non-scure memory for OPTEE public memory */
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{
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TZASC_REGION_SECURITY_SRW,
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TZASC_REGION_ENABLED,
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0xFF800000,
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0x0,
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TZASC_REGION_SIZE_8MB,
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0xC0, /* Disable region 6 & 7 */
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},
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{}
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};
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#endif /* SOC_TZASC_H */
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