106 lines
2.4 KiB
C
106 lines
2.4 KiB
C
/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <platform_def.h>
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#include <bl1/bl1.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/sp805.h>
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#include <drivers/console.h>
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#include <plat/common/platform.h>
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#include <plat_marvell.h>
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/* Weak definitions may be overridden in specific Marvell standard platform */
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#pragma weak bl1_early_platform_setup
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#pragma weak bl1_plat_arch_setup
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#pragma weak bl1_platform_setup
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#pragma weak bl1_plat_sec_mem_layout
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/* Data structure which holds the extents of the RAM for BL1*/
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static meminfo_t bl1_ram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_ram_layout;
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}
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/*
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* BL1 specific platform actions shared between Marvell standard platforms.
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*/
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void marvell_bl1_early_platform_setup(void)
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{
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/* Initialize the console to provide early debug support */
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marvell_console_boot_init();
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_ram_layout.total_base = MARVELL_BL_RAM_BASE;
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bl1_ram_layout.total_size = MARVELL_BL_RAM_SIZE;
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}
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void bl1_early_platform_setup(void)
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{
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marvell_bl1_early_platform_setup();
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}
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/*
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* Perform the very early platform specific architecture setup shared between
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* MARVELL standard platforms. This only does basic initialization. Later
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* architectural setup (bl1_arch_setup()) does not do anything platform
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* specific.
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*/
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void marvell_bl1_plat_arch_setup(void)
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{
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marvell_setup_page_tables(bl1_ram_layout.total_base,
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bl1_ram_layout.total_size,
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BL1_RO_BASE,
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BL1_RO_LIMIT,
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BL1_RO_DATA_BASE,
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BL1_RO_DATA_END
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#if USE_COHERENT_MEM
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, BL_COHERENT_RAM_BASE,
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BL_COHERENT_RAM_END
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#endif
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);
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enable_mmu_el3(0);
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}
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void bl1_plat_arch_setup(void)
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{
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marvell_bl1_plat_arch_setup();
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}
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/*
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* Perform the platform specific architecture setup shared between
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* MARVELL standard platforms.
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*/
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void marvell_bl1_platform_setup(void)
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{
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/* Initialise the IO layer and register platform IO devices */
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plat_marvell_io_setup();
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}
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void bl1_platform_setup(void)
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{
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marvell_bl1_platform_setup();
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}
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void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
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{
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#ifdef EL3_PAYLOAD_BASE
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/*
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* Program the EL3 payload's entry point address into the CPUs mailbox
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* in order to release secondary CPUs from their holding pen and make
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* them jump there.
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*/
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marvell_program_trusted_mailbox(ep_info->pc);
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dsbsy();
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sev();
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#endif
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}
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