156 lines
3.8 KiB
C
156 lines
3.8 KiB
C
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MCUCFG_H
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#define MCUCFG_H
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#include <stdint.h>
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#include <platform_def.h>
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struct mt6795_mcucfg_regs {
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uint32_t mp0_ca7l_cache_config;
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struct {
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uint32_t mem_delsel0;
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uint32_t mem_delsel1;
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} mp0_cpu[4];
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uint32_t mp0_cache_mem_delsel0;
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uint32_t mp0_cache_mem_delsel1;
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uint32_t mp0_axi_config;
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uint32_t mp0_misc_config[2];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp0_rv_addr[4];
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uint32_t mp0_ca7l_cfg_dis;
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uint32_t mp0_ca7l_clken_ctrl;
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uint32_t mp0_ca7l_rst_ctrl;
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uint32_t mp0_ca7l_misc_config;
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uint32_t mp0_ca7l_dbg_pwr_ctrl;
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uint32_t mp0_rw_rsvd0;
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uint32_t mp0_rw_rsvd1;
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uint32_t mp0_ro_rsvd;
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uint32_t reserved0_0[100];
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uint32_t mp1_cpucfg;
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uint32_t mp1_miscdbg;
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uint32_t reserved0_1[13];
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uint32_t mp1_rst_ctl;
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uint32_t mp1_clkenm_div;
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uint32_t reserved0_2[7];
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uint32_t mp1_config_res;
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uint32_t reserved0_3[13];
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struct {
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uint32_t rv_addr_lw;
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uint32_t rv_addr_hw;
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} mp1_rv_addr[2];
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uint32_t reserved0_4[84];
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uint32_t mp0_rst_status; /* 0x400 */
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uint32_t mp0_dbg_ctrl;
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uint32_t mp0_dbg_flag;
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uint32_t mp0_ca7l_ir_mon;
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struct {
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uint32_t pc_lw;
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uint32_t pc_hw;
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uint32_t fp_arch32;
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uint32_t sp_arch32;
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uint32_t fp_arch64_lw;
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uint32_t fp_arch64_hw;
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uint32_t sp_arch64_lw;
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uint32_t sp_arch64_hw;
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} mp0_dbg_core[4];
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uint32_t dfd_ctrl;
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uint32_t dfd_cnt_l;
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uint32_t dfd_cnt_h;
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uint32_t misccfg_mp0_rw_rsvd;
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uint32_t misccfg_sec_vio_status0;
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uint32_t misccfg_sec_vio_status1;
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uint32_t reserved1[22];
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uint32_t misccfg_rw_rsvd; /* 0x500 */
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uint32_t mcusys_dbg_mon_sel_a;
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uint32_t mcusys_dbg_mon;
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uint32_t reserved2[61];
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uint32_t mcusys_config_a; /* 0x600 */
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uint32_t mcusys_config1_a;
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uint32_t mcusys_gic_peribase_a;
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uint32_t reserved3;
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uint32_t sec_range0_start; /* 0x610 */
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uint32_t sec_range0_end;
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uint32_t sec_range_enable;
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uint32_t reserved4;
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uint32_t int_pol_ctl[8]; /* 0x620 */
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uint32_t aclken_div; /* 0x640 */
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uint32_t pclken_div;
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uint32_t l2c_sram_ctrl;
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uint32_t armpll_jit_ctrl;
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uint32_t cci_addrmap; /* 0x650 */
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uint32_t cci_config;
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uint32_t cci_periphbase;
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uint32_t cci_nevntcntovfl;
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uint32_t cci_clk_ctrl; /* 0x660 */
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uint32_t cci_acel_s1_ctrl;
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uint32_t bus_fabric_dcm_ctrl;
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uint32_t reserved5;
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uint32_t xgpt_ctl; /* 0x670 */
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uint32_t xgpt_idx;
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uint32_t ptpod2_ctl0;
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uint32_t ptpod2_ctl1;
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uint32_t mcusys_revid;
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uint32_t mcusys_rw_rsvd0;
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uint32_t mcusys_rw_rsvd1;
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};
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static struct mt6795_mcucfg_regs *const mt6795_mcucfg = (void *)MCUCFG_BASE;
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/* cpu boot mode */
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#define MP0_CPUCFG_64BIT_SHIFT 12
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#define MP1_CPUCFG_64BIT_SHIFT 28
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#define MP0_CPUCFG_64BIT (U(0xf) << MP0_CPUCFG_64BIT_SHIFT)
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#define MP1_CPUCFG_64BIT (U(0xf) << MP1_CPUCFG_64BIT_SHIFT)
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/* scu related */
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enum {
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MP0_ACINACTM_SHIFT = 4,
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MP1_ACINACTM_SHIFT = 0,
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MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
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MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
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};
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enum {
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
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MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
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MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
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0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
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};
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enum {
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MP1_AINACTS_SHIFT = 4,
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MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
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};
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enum {
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MP1_SW_CG_GEN_SHIFT = 12,
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MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
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};
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enum {
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MP1_L2RSTDISABLE_SHIFT = 14,
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MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
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};
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#endif /* MCUCFG_H */
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