239 lines
9.4 KiB
C
239 lines
9.4 KiB
C
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <lib/utils_def.h>
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#define PLAT_PRIMARY_CPU 0x0
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define IO_PHYS (0x10000000)
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#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
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#define MCUCFG_BASE (IO_PHYS + 0x200000)
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#define PERI_BASE (IO_PHYS + 0x1000000)
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#define GPIO_BASE (IO_PHYS + 0x370000)
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#define SPM_BASE (IO_PHYS + 0x6000)
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#define RGU_BASE (MCUCFG_BASE + 0x11000)
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#define PMIC_WRAP_BASE (IO_PHYS + 0x10000)
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#define TRNG_base (MCUCFG_BASE + 0x230000)
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#define MT_GIC_BASE (0x10220000)
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#define MCU_SYS_SIZE (0x700000)
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#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
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/* Aggregate of all devices in the first GB */
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#define MTK_DEV_RNG0_BASE IO_PHYS
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#define MTK_DEV_RNG0_SIZE 0x400000
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#define MTK_DEV_RNG1_BASE (PERI_BASE)
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#define MTK_DEV_RNG1_SIZE 0x4000000
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (PERI_BASE + 0x2000)
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#define UART_BAUDRATE (921600)
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#define UART_CLOCK (26000000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 13000000
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#define SYS_COUNTER_FREQ_IN_MHZ (SYS_COUNTER_FREQ_IN_TICKS/1000000)
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE+0x1000)
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#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
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#define BASE_GICR_BASE (MT_GIC_BASE + 0x200000)
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#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
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#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
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#define INT_POL_CTL0 0x10200620
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#define GIC_PRIVATE_SIGNALS (32)
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
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#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
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/*******************************************************************************
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* WDT Registers
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******************************************************************************/
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#define MTK_WDT_BASE (RGU_BASE)
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#define MTK_WDT_SIZE (0x1000)
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#define MTK_WDT_MODE (MTK_WDT_BASE+0x0000)
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#define MTK_WDT_LENGTH (MTK_WDT_BASE+0x0004)
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#define MTK_WDT_RESTART (MTK_WDT_BASE+0x0008)
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#define MTK_WDT_STATUS (MTK_WDT_BASE+0x000C)
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#define MTK_WDT_INTERVAL (MTK_WDT_BASE+0x0010)
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#define MTK_WDT_SWRST (MTK_WDT_BASE+0x0014)
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#define MTK_WDT_SWSYSRST (MTK_WDT_BASE+0x0018)
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#define MTK_WDT_NONRST_REG (MTK_WDT_BASE+0x0020)
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#define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE+0x0024)
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#define MTK_WDT_REQ_MODE (MTK_WDT_BASE+0x0030)
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#define MTK_WDT_REQ_IRQ_EN (MTK_WDT_BASE+0x0034)
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#define MTK_WDT_DEBUG_CTL (MTK_WDT_BASE+0x0040)
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/*WDT_STATUS*/
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#define MTK_WDT_STATUS_HWWDT_RST (0x80000000)
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#define MTK_WDT_STATUS_SWWDT_RST (0x40000000)
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#define MTK_WDT_STATUS_IRQWDT_RST (0x20000000)
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#define MTK_WDT_STATUS_DEBUGWDT_RST (0x00080000)
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#define MTK_WDT_STATUS_SPMWDT_RST (0x0002)
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#define MTK_WDT_STATUS_SPM_THERMAL_RST (0x0001)
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#define MTK_WDT_STATUS_THERMAL_DIRECT_RST (1<<18)
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#define MTK_WDT_STATUS_SECURITY_RST (1<<28)
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#define MTK_WDT_MODE_DUAL_MODE 0x0040
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#define MTK_WDT_MODE_IRQ 0x0008
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#define MTK_WDT_MODE_KEY 0x22000000
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#define MTK_WDT_MODE_EXTEN 0x0004
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#define MTK_WDT_SWRST_KEY 0x1209
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#define MTK_WDT_RESTART_KEY (0x1971)
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/* FIQ platform related define */
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#define MT_IRQ_SEC_SGI_0 8
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#define MT_IRQ_SEC_SGI_1 9
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#define MT_IRQ_SEC_SGI_2 10
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#define MT_IRQ_SEC_SGI_3 11
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#define MT_IRQ_SEC_SGI_4 12
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#define MT_IRQ_SEC_SGI_5 13
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#define MT_IRQ_SEC_SGI_6 14
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#define MT_IRQ_SEC_SGI_7 15
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#define FIQ_SMP_CALL_SGI MT_IRQ_SEC_SGI_5
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL1)
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#define PLATFORM_STACK_SIZE 0x440
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#elif defined(IMAGE_BL2)
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#define PLATFORM_STACK_SIZE 0x400
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x800
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#elif defined(IMAGE_BL32)
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#define PLATFORM_STACK_SIZE 0x440
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#endif
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLAT_MAX_PWR_LVL U(2) /* MPIDR_AFFLVL2 */
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(2)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
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PLATFORM_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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/* ATF Argument */
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#define ATF_ARG_SIZE (0x800)
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/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */
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#define TZRAM_BASE (0x110000)
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#if DEBUG
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#define TZRAM_SIZE (0x1C400)
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#else
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#define TZRAM_SIZE (0x1C400)
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#endif
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#define TZRAM2_BASE 0x00100000
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#define TZRAM2_SIZE 0xDC00
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#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
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#define RAM_CONSOLE_BASE 0x0012D000
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#define RAM_CONSOLE_SIZE 0x00001000
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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#define BSS1_STACK_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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#define BL31_TZRAM_SIZE (TZRAM_SIZE - ATF_ARG_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
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#define MAX_XLAT_TABLES 7
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* CCI-400 related constants
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******************************************************************************/
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#define CCI400_BASE 0x10390000
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#define CCI400_SL_IFACE_CLUSTER0 4
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#define CCI400_SL_IFACE_CLUSTER1 3
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#define CCI400_SL_IFACE_INDEX(mpidr) (mpidr & MPIDR_CLUSTER_MASK ? \
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CCI400_SL_IFACE_CLUSTER1 : \
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CCI400_SL_IFACE_CLUSTER0)
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#define CCI_SEC_ACCESS_OFFSET (0x8)
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#define BL32_BASE (0x0)
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/*
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* Load address of BL3-3 for this platform port
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*/
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#define LK_SIZE_LIMIT (0x100000)
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#define PLAT_MTK_NS_IMAGE_OFFSET (0x41E00000)
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/* 16KB */
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#define ATF_AEE_BUFFER_SIZE (0x4000)
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#define PAGE_SIZE_2MB_MASK (PAGE_SIZE_2MB - 1)
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#define IS_PAGE_2MB_ALIGNED(addr) (((addr) & PAGE_SIZE_2MB_MASK) == 0)
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#define PAGE_SIZE_2MB (1 << PAGE_SIZE_2MB_SHIFT)
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#define PAGE_SIZE_2MB_SHIFT TWO_MB_SHIFT
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#endif /* PLATFORM_DEF_H */
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