367 lines
9.3 KiB
C
367 lines
9.3 KiB
C
/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <cortex_a53.h>
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#include <cortex_a73.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <mcucfg.h>
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#include <spm.h>
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#include <drivers/delay_timer.h>
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#include <mtspmc.h>
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#include "mtspmc_private.h"
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static void set_retention(int cluster, int tick)
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{
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uint64_t cpuectlr;
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if (cluster)
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cpuectlr = read_a73_cpuectlr_el1();
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else
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cpuectlr = read_a53_cpuectlr_el1();
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cpuectlr &= ~0x7ULL;
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cpuectlr |= tick & 0x7;
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if (cluster)
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write_a73_cpuectlr_el1(cpuectlr);
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else
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write_a53_cpuectlr_el1(cpuectlr);
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}
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void spm_enable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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set_retention(cluster, 1);
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mmio_clrbits_32(reg, SW_NO_WAIT_Q);
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}
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void spm_disable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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mmio_setbits_32(reg, SW_NO_WAIT_Q);
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set_retention(cluster, 0);
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}
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void spm_set_cpu_power_off(int cluster, int cpu)
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{
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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}
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void spm_enable_cluster_auto_off(int cluster)
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{
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assert(cluster);
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mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q);
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mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0));
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN);
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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}
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void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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mmio_write_32(reg, bootaddr);
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}
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uintptr_t mcucfg_get_bootaddr(int cluster, int cpu)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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return mmio_read_32(reg);
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}
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void mcucfg_init_archstate(int cluster, int cpu, int arm64)
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{
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uintptr_t reg;
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int i;
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reg = per_cluster(cluster, MCUCFG_INITARCH);
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i = cluster ? 16 : 12;
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mmio_setbits_32(reg, (arm64 & 1) << (i + cpu));
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}
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/**
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* Return power state of specified subsystem
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*
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* @mask: mask to SPM_PWR_STATUS to query the power state
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* of one subsystem.
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* RETURNS:
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* 0 (the subsys was powered off)
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* 1 (the subsys was powered on)
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*/
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int spm_get_powerstate(uint32_t mask)
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{
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return mmio_read_32(SPM_PWR_STATUS) & mask;
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}
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int spm_get_cluster_powerstate(int cluster)
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{
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uint32_t mask;
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mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;
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return spm_get_powerstate(mask);
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}
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int spm_get_cpu_powerstate(int cluster, int cpu)
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{
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uint32_t i;
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/*
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* a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS
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* register which are the BITS[9:12](MP0_CPU0~3) and
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* BITS[16:19](MP1_CPU0~3)
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*/
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i = (cluster) ? 16 : 9;
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i = 1 << (i + cpu);
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return spm_get_powerstate(i);
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}
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int spmc_init(void)
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{
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/* enable SPM register control */
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mmio_write_32(SPM_POWERON_CONFIG_EN,
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PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN);
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#if SPMC_MODE == 1
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INFO("SPM: enable SPMC mode\n");
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/* 0: SPMC mode 1: Legacy mode */
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mmio_write_32(SPM_BYPASS_SPMC, 0);
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mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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#endif
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B);
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS);
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mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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return 0;
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}
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/**
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* Power on a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered on
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* @cpu: the CPU ID of the CPU which to be powered on
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*/
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void spm_poweron_cpu(int cluster, int cpu)
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{
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INFO("spmc: power on core %d.%d\n", cluster, cpu);
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/* STA_POWER_ON */
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/* Start to turn on MP0_CPU0 */
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 1 */
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while (!spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Finish to turn on MP0_CPU0 */
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INFO("spmc: power on core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered off
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* @cpu: the CPU ID of the CPU which to be powered off
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*/
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void spm_poweroff_cpu(int cluster, int cpu)
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{
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INFO("spmc: power off core %d.%d\n", cluster, cpu);
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/* Start to turn off MP0_CPU0 */
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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/* Set PWR_ON = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 0 */
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while (spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Set PWR_RST_B = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Finish to turn off MP0_CPU0 */
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INFO("spmc: power off core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a cluster with specified index
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*
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* @cluster: the cluster index which to be powered off
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*/
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void spm_poweroff_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power off cluster %d\n", cluster);
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/* Start to turn off MP0_CPUTOP */
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/* Set bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);
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while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)
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;
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* SPMC_DORMANT_ENABLE[0]=0 */
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mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);
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/* Set PWR_ON = 0" */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */
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while (spm_get_cluster_powerstate(cluster))
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;
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK);
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}
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/* CPU_EXT_BUCK_ISO[0]=1 */
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if (cluster)
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mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* Finish to turn off MP0_CPUTOP */
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INFO("spmc: power off cluster %d successfully\n", cluster);
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}
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/**
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* Power on a cluster with specified index
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*
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* @cluster: the cluster index which to be powered on
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*/
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void spm_poweron_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power on cluster %d\n", cluster);
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/* Start to turn on MP1_CPUTOP */
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B);
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/* CPU_EXT_BUCK_ISO[1]=0 */
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/* Set mp<n>_vproc_ext_off to 0 to release vproc isolation control */
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mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK);
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}
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_RST_B);
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/* Set PWR_CLK_DIS = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_CLK_DIS);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */
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while (!spm_get_cluster_powerstate(cluster))
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;
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/* Release bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);
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/* Finish to turn on MP1_CPUTOP */
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INFO("spmc: power on cluster %d successfully\n", cluster);
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}
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