234 lines
8.4 KiB
C
234 lines
8.4 KiB
C
/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef MTSPMC_PRIVATE_H
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#define MTSPMC_PRIVATE_H
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/*
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* per_cpu/cluster helper
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*/
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struct per_cpu_reg {
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int cluster_addr;
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int cpu_stride;
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};
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#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
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(cpu << reg[cluster].cpu_stride))
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#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
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/* SPMC related registers */
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#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
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/* bit-fields of SPM_POWERON_CONFIG_EN */
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#define BCLK_CG_EN (1 << 0)
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#define MD_BCLK_CG_EN (1 << 1)
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#define PROJECT_CODE (0xb16 << 16)
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#define SPM_PWR_STATUS (SPM_BASE + 0x180)
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#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
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#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
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#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
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#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
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#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
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#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
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#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
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#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
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#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
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#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
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#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
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#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
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#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
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#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
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#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
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#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
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#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
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#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
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#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
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#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
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#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
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#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
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#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
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#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
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#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
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#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
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/* bit-fields of SPM_CPU_EXT_BUCK_ISO */
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#define MP0_EXT_BUCK_ISO (1 << 0)
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#define MP1_EXT_BUCK_ISO (1 << 1)
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#define MP_EXT_BUCK_ISO (1 << 2)
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/* bit-fields of SPM_PWR_STATUS */
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#define PWR_STATUS_MD (1 << 0)
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#define PWR_STATUS_CONN (1 << 1)
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#define PWR_STATUS_DDRPHY (1 << 2)
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#define PWR_STATUS_DISP (1 << 3)
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#define PWR_STATUS_MFG (1 << 4)
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#define PWR_STATUS_ISP (1 << 5)
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#define PWR_STATUS_INFRA (1 << 6)
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#define PWR_STATUS_VDEC (1 << 7)
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#define PWR_STATUS_MP0_CPUTOP (1 << 8)
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#define PWR_STATUS_MP0_CPU0 (1 << 9)
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#define PWR_STATUS_MP0_CPU1 (1 << 10)
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#define PWR_STATUS_MP0_CPU2 (1 << 11)
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#define PWR_STATUS_MP0_CPU3 (1 << 12)
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#define PWR_STATUS_MCUSYS (1 << 14)
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#define PWR_STATUS_MP1_CPUTOP (1 << 15)
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#define PWR_STATUS_MP1_CPU0 (1 << 16)
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#define PWR_STATUS_MP1_CPU1 (1 << 17)
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#define PWR_STATUS_MP1_CPU2 (1 << 18)
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#define PWR_STATUS_MP1_CPU3 (1 << 19)
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#define PWR_STATUS_VEN (1 << 21)
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#define PWR_STATUS_MFG_ASYNC (1 << 23)
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#define PWR_STATUS_AUDIO (1 << 24)
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#define PWR_STATUS_C2K (1 << 28)
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#define PWR_STATUS_MD_INFRA (1 << 29)
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/* bit-fields of SPM_*_PWR_CON */
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#define PWRCTRL_PWR_RST_B (1 << 0)
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#define PWRCTRL_PWR_ISO (1 << 1)
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#define PWRCTRL_PWR_ON (1 << 2)
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#define PWRCTRL_PWR_ON_2ND (1 << 3)
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#define PWRCTRL_PWR_CLK_DIS (1 << 4)
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#define PWRCTRL_PWR_SRAM_CKISO (1 << 5)
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#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6)
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#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7)
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#define PWRCTRL_PWR_SRAM_PDN (1 << 8)
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#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12)
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#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24)
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#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28)
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/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */
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static const struct per_cpu_reg SPM_CPU_PWR[] = {
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[0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
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[1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
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};
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/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */
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static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
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[0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
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[1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
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};
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/* APB Module infracfg_ao */
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#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
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#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
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#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
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#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
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/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */
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#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \
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(1 << 13)|(1 << 26))
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#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \
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(1 << 15)|(1 << 27))
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/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */
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#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \
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(1 << 13)|(1 << 26))
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#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \
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(1 << 15)|(1 << 27))
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/*
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* MCU configuration registers
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*/
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/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
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#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
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#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
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#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2)
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#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3)
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#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
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#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
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#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
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#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
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#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2])
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#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3])
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#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
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/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */
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#define CPU0_SPARK_VRET_CTRL (0x3f << 0)
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#define CPU1_SPARK_VRET_CTRL (0x3f << 8)
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#define CPU2_SPARK_VRET_CTRL (0x3f << 16)
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#define CPU3_SPARK_VRET_CTRL (0x3f << 24)
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/* SPARK control in little cores */
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#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
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#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
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#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
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#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
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/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */
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#define SW_SPARK_EN (1 << 0)
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#define SW_NO_WAIT_Q (1 << 1)
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/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */
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#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
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#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8)
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/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */
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#define SW_RST_B (1 << 0)
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#define TOPAON_APB_MASK (1 << 1)
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#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208)
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#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290)
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#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298)
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#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0)
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#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8)
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/* SPMC control */
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#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
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#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0)
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#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC)
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/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */
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static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
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[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 },
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};
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/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */
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static const struct per_cpu_reg MCUCFG_INITARCH[] = {
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[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
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[1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
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};
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/* SPARK control in BIG cores */
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#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430)
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#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434)
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#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438)
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#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c)
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#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440)
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#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444)
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#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448)
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#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c)
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/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */
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#define SW_SPARK_EN (1 << 0)
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#define SW_NO_WAIT_Q (1 << 1)
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#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700)
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/* bit-fields of MCUCFG_MP2_SPARK2LDO */
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#define SPARK_VRET_CTRL (0x3f << 0)
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#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6)
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#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10)
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#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14)
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#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18)
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/* per_cpu registers for SPARK */
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static const struct per_cpu_reg MCUCFG_SPARK[] = {
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[0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 },
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[1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 },
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};
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/* per_cpu registers for SPARK2LDO */
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static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = {
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[0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
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[1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO },
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};
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#endif /* MTSPMC_PRIVATE_H */
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