161 lines
3.8 KiB
C
161 lines
3.8 KiB
C
/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <bl31/interrupt_mgmt.h>
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#include <mt_gic_v3.h>
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#include <mtk_plat_common.h>
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#include "../drivers/arm/gic/v3/gicv3_private.h"
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#include "plat_private.h"
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <stdio.h>
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uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
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/* we save and restore the GICv3 context on system suspend */
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gicv3_dist_ctx_t dist_ctx;
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static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
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{
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return plat_core_pos_by_mpidr(mpidr);
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}
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gicv3_driver_data_t mt_gicv3_data = {
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.gicd_base = MT_GIC_BASE,
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.gicr_base = MT_GIC_RDIST_BASE,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = mt_mpidr_to_core_pos,
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};
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struct gic_chip_data {
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unsigned int saved_group;
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unsigned int saved_enable;
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unsigned int saved_conf0;
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unsigned int saved_conf1;
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unsigned int saved_grpmod;
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};
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static struct gic_chip_data gic_data;
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void clear_sec_pol_ctl_en(void)
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{
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unsigned int i;
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/* total 19 polarity ctrl registers */
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for (i = 0; i <= NR_INT_POL_CTL - 1; i++) {
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mmio_write_32((SEC_POL_CTL_EN0 + (i * 4)), 0);
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}
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dsb();
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}
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void mt_gic_driver_init(void)
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{
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gicv3_driver_init(&mt_gicv3_data);
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}
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void mt_gic_set_pending(uint32_t irq)
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{
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gicv3_set_interrupt_pending(irq, plat_my_core_pos());
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}
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void mt_gic_cpuif_enable(void)
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{
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gicv3_cpuif_enable(plat_my_core_pos());
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}
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void mt_gic_cpuif_disable(void)
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{
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gicv3_cpuif_disable(plat_my_core_pos());
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}
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void mt_gic_rdistif_init(void)
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{
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unsigned int proc_num;
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unsigned int index;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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/* set all SGI/PPI as non-secure GROUP1 by default */
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mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
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mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
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/* setup the default PPI/SGI priorities */
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for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
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gicr_write_ipriorityr(gicr_base, index,
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GICD_IPRIORITYR_DEF_VAL);
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}
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void mt_gic_distif_save(void)
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{
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gicv3_distif_save(&dist_ctx);
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}
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void mt_gic_distif_restore(void)
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{
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gicv3_distif_init_restore(&dist_ctx);
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}
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void mt_gic_rdistif_save(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
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gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
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gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
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gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
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gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
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rdist_has_saved[proc_num] = 1;
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}
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void mt_gic_rdistif_restore(void)
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{
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unsigned int proc_num;
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uintptr_t gicr_base;
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proc_num = plat_my_core_pos();
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if (rdist_has_saved[proc_num] == 1) {
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gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
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mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
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mmio_write_32(gicr_base + GICR_ISENABLER0, gic_data.saved_enable);
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mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
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mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
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mmio_write_32(gicr_base + GICR_IGRPMODR0, gic_data.saved_grpmod);
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}
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}
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void mt_gic_sync_dcm_enable(void)
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{
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mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_ON);
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}
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void mt_gic_sync_dcm_disable(void)
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{
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mmio_clrsetbits_32(GIC_SYNC_DCM, GIC_SYNC_DCM_MASK, GIC_SYNC_DCM_OFF);
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}
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void mt_gic_init(void)
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{
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gicv3_distif_init();
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gicv3_cpuif_enable(plat_my_core_pos());
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mt_gic_rdistif_init();
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clear_sec_pol_ctl_en();
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}
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