327 lines
14 KiB
C
327 lines
14 KiB
C
/*
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* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef TEGRA_DEF_H
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#define TEGRA_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* Platform BL31 specific defines.
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******************************************************************************/
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#define BL31_SIZE U(0x40000)
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/*******************************************************************************
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* Chip specific cluster and cpu numbers
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******************************************************************************/
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#define PLATFORM_CLUSTER_COUNT U(4)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(2)
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/*******************************************************************************
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* Chip specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
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/*******************************************************************************
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* These values are used by the PSCI implementation during the `CPU_SUSPEND`
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* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
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* parameter.
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******************************************************************************/
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#define PSTATE_ID_CORE_IDLE U(6)
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#define PSTATE_ID_CORE_POWERDN U(7)
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#define PSTATE_ID_SOC_POWERDN U(2)
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/*******************************************************************************
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* Platform power states (used by PSCI framework)
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*
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* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
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* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
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******************************************************************************/
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(8)
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/*******************************************************************************
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* Secure IRQ definitions
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******************************************************************************/
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#define TEGRA194_MAX_SEC_IRQS U(2)
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#define TEGRA194_TOP_WDT_IRQ U(49)
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#define TEGRA194_AON_WDT_IRQ U(50)
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#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
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/*******************************************************************************
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* Clock identifier for the SE device
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******************************************************************************/
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#define TEGRA194_CLK_SE U(124)
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#define TEGRA_CLK_SE TEGRA194_CLK_SE
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/*******************************************************************************
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* Tegra Miscellanous register constants
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x00100000)
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#define HARDWARE_REVISION_OFFSET U(0x4)
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#define MISCREG_EMU_REVID U(0x3160)
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#define BOARD_MASK_BITS U(0xFF)
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#define BOARD_SHIFT_BITS U(24)
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#define MISCREG_PFCFG U(0x200C)
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/*******************************************************************************
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* Tegra General Purpose Centralised DMA constants
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******************************************************************************/
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#define TEGRA_GPCDMA_BASE U(0x02610000)
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/*******************************************************************************
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* Tegra Memory Controller constants
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******************************************************************************/
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#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
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#define TEGRA_MC_BASE U(0x02C10000)
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/* General Security Carveout register macros */
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#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
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#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
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#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
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#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
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#define MC_GSC_BASE_LO_SHIFT U(12)
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#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
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#define MC_GSC_BASE_HI_SHIFT U(0)
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#define MC_GSC_BASE_HI_MASK U(3)
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#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
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/* TZDRAM carveout configuration registers */
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#define MC_SECURITY_CFG0_0 U(0x70)
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#define MC_SECURITY_CFG1_0 U(0x74)
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#define MC_SECURITY_CFG3_0 U(0x9BC)
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#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
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#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
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#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
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#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154)
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#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0)
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#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0)
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#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1)
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/* Video Memory carveout configuration registers */
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#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
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#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
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#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
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#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
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#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
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/*
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* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
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* non-overlapping Video memory region
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*/
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#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
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#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
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#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
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#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
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#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
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/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
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#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
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#define MC_TZRAM_BASE_LO U(0x2194)
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#define MC_TZRAM_BASE_HI U(0x2198)
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#define MC_TZRAM_SIZE U(0x219C)
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#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
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#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
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#define TZRAM_ALLOW_MPCORER (U(1) << 7)
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#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
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/* Memory Controller Reset Control registers */
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#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
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#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
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#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
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#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
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/*******************************************************************************
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* Tegra UART Controller constants
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******************************************************************************/
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#define TEGRA_UARTA_BASE U(0x03100000)
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#define TEGRA_UARTB_BASE U(0x03110000)
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#define TEGRA_UARTC_BASE U(0x0C280000)
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#define TEGRA_UARTD_BASE U(0x03130000)
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#define TEGRA_UARTE_BASE U(0x03140000)
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#define TEGRA_UARTF_BASE U(0x03150000)
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#define TEGRA_UARTG_BASE U(0x0C290000)
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/*******************************************************************************
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* XUSB PADCTL
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******************************************************************************/
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#define TEGRA_XUSB_PADCTL_BASE U(0x03520000)
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#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
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#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
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#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
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#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
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#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
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#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
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#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
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/*******************************************************************************
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* Tegra Fuse Controller related constants
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******************************************************************************/
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#define TEGRA_FUSE_BASE U(0x03820000)
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#define OPT_SUBREVISION U(0x248)
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#define SUBREVISION_MASK U(0xF)
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/*******************************************************************************
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* GICv2 & interrupt handling related constants
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******************************************************************************/
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#define TEGRA_GICD_BASE U(0x03881000)
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#define TEGRA_GICC_BASE U(0x03882000)
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/*******************************************************************************
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* Security Engine related constants
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******************************************************************************/
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#define TEGRA_SE0_BASE U(0x03AC0000)
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#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
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#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
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#define TEGRA_PKA1_BASE U(0x03AD0000)
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#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
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#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
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#define TEGRA_RNG1_BASE U(0x03AE0000)
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#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
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/*******************************************************************************
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* Tegra HSP doorbell #0 constants
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******************************************************************************/
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#define TEGRA_HSP_DBELL_BASE U(0x03C90000)
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#define HSP_DBELL_1_ENABLE U(0x104)
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#define HSP_DBELL_3_TRIGGER U(0x300)
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#define HSP_DBELL_3_ENABLE U(0x304)
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/*******************************************************************************
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* Tegra hardware synchronization primitives for the SPE engine
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******************************************************************************/
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#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
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#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
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/*******************************************************************************
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* Tegra micro-seconds timer constants
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******************************************************************************/
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#define TEGRA_TMRUS_BASE U(0x0C2E0000)
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#define TEGRA_TMRUS_SIZE U(0x10000)
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/*******************************************************************************
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* Tegra Power Mgmt Controller constants
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******************************************************************************/
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#define TEGRA_PMC_BASE U(0x0C360000)
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/*******************************************************************************
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* Tegra scratch registers constants
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******************************************************************************/
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#define TEGRA_SCRATCH_BASE U(0x0C390000)
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#define SECURE_SCRATCH_RSV68_LO U(0x284)
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#define SECURE_SCRATCH_RSV68_HI U(0x288)
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#define SECURE_SCRATCH_RSV69_LO U(0x28C)
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#define SECURE_SCRATCH_RSV69_HI U(0x290)
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#define SECURE_SCRATCH_RSV70_LO U(0x294)
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#define SECURE_SCRATCH_RSV70_HI U(0x298)
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#define SECURE_SCRATCH_RSV71_LO U(0x29C)
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#define SECURE_SCRATCH_RSV71_HI U(0x2A0)
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#define SECURE_SCRATCH_RSV72_LO U(0x2A4)
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#define SECURE_SCRATCH_RSV72_HI U(0x2A8)
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#define SECURE_SCRATCH_RSV75 U(0x2BC)
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#define SECURE_SCRATCH_RSV81_LO U(0x2EC)
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#define SECURE_SCRATCH_RSV81_HI U(0x2F0)
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#define SECURE_SCRATCH_RSV97 U(0x36C)
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#define SECURE_SCRATCH_RSV99_LO U(0x37C)
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#define SECURE_SCRATCH_RSV99_HI U(0x380)
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#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
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#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
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#define SCRATCH_BL31_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75
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#define SCRATCH_BL31_PARAMS_HI_ADDR_MASK U(0xFFFF)
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#define SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT U(0)
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#define SCRATCH_BL31_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_LO
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#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR SECURE_SCRATCH_RSV75
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#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK U(0xFFFF0000)
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#define SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT U(16)
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#define SCRATCH_BL31_PLAT_PARAMS_LO_ADDR SECURE_SCRATCH_RSV81_HI
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#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
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#define SCRATCH_MC_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
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#define SCRATCH_MC_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
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#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
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#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
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/*******************************************************************************
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* Tegra Memory Mapped Control Register Access Bus constants
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******************************************************************************/
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#define TEGRA_MMCRAB_BASE U(0x0E000000)
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/*******************************************************************************
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* Tegra SMMU Controller constants
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******************************************************************************/
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#define TEGRA_SMMU0_BASE U(0x12000000)
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#define TEGRA_SMMU1_BASE U(0x11000000)
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#define TEGRA_SMMU2_BASE U(0x10000000)
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/*******************************************************************************
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* Tegra TZRAM constants
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******************************************************************************/
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#define TEGRA_TZRAM_BASE U(0x40000000)
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#define TEGRA_TZRAM_SIZE U(0x40000)
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/*******************************************************************************
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* Tegra CCPLEX-BPMP IPC constants
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******************************************************************************/
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#define TEGRA_BPMP_IPC_TX_PHYS_BASE U(0x4004C000)
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#define TEGRA_BPMP_IPC_RX_PHYS_BASE U(0x4004D000)
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#define TEGRA_BPMP_IPC_CH_MAP_SIZE U(0x1000) /* 4KB */
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/*******************************************************************************
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* Tegra Clock and Reset Controller constants
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******************************************************************************/
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#define TEGRA_CAR_RESET_BASE U(0x20000000)
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#define TEGRA_GPU_RESET_REG_OFFSET U(0x18)
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#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C)
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#define GPU_RESET_BIT (U(1) << 0)
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#define GPU_SET_BIT (U(1) << 0)
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#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
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#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
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/*******************************************************************************
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* Tegra DRAM memory base address
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******************************************************************************/
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#define TEGRA_DRAM_BASE ULL(0x80000000)
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#define TEGRA_DRAM_END ULL(0xFFFFFFFFF)
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/*******************************************************************************
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* XUSB STREAMIDs
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******************************************************************************/
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#define TEGRA_SID_XUSB_HOST U(0x1b)
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#define TEGRA_SID_XUSB_DEV U(0x1c)
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#define TEGRA_SID_XUSB_VF0 U(0x5d)
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#define TEGRA_SID_XUSB_VF1 U(0x5e)
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#define TEGRA_SID_XUSB_VF2 U(0x5f)
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#define TEGRA_SID_XUSB_VF3 U(0x60)
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/*******************************************************************************
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* SCR addresses and expected settings
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******************************************************************************/
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#define SCRATCH_RSV68_SCR U(0x0C398110)
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#define SCRATCH_RSV68_SCR_VAL U(0x38000101)
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#define SCRATCH_RSV71_SCR U(0x0C39811C)
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#define SCRATCH_RSV71_SCR_VAL U(0x38000101)
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#define SCRATCH_RSV72_SCR U(0x0C398120)
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#define SCRATCH_RSV72_SCR_VAL U(0x38000101)
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#define SCRATCH_RSV75_SCR U(0x0C39812C)
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#define SCRATCH_RSV75_SCR_VAL U(0x3A000005)
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#define SCRATCH_RSV81_SCR U(0x0C398144)
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#define SCRATCH_RSV81_SCR_VAL U(0x3A000105)
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#define SCRATCH_RSV97_SCR U(0x0C398184)
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#define SCRATCH_RSV97_SCR_VAL U(0x38000101)
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#define SCRATCH_RSV99_SCR U(0x0C39818C)
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#define SCRATCH_RSV99_SCR_VAL U(0x38000101)
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#define SCRATCH_RSV109_SCR U(0x0C3981B4)
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#define SCRATCH_RSV109_SCR_VAL U(0x38000101)
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#define MISCREG_SCR_SCRTZWELCK U(0x00109000)
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#define MISCREG_SCR_SCRTZWELCK_VAL U(0x30000100)
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#endif /* TEGRA_DEF_H */
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