230 lines
4.5 KiB
ArmAsm
230 lines
4.5 KiB
ArmAsm
/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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.section .text, "ax"
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#include <asm_macros.S>
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#ifndef NXP_COINED_BB
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#include <flash_info.h>
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#include <fspi.h>
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#endif
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#include <regs.h>
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#ifdef NXP_COINED_BB
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#include <snvs.h>
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#endif
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#include <plat_warm_rst.h>
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#include <platform_def.h>
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#define SDRAM_CFG 0x110
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#define SDRAM_CFG_2 0x114
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#define SDRAM_MD_CNTL 0x120
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#define SDRAM_INTERVAL 0x124
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#define TIMING_CFG_10 0x258
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#define DEBUG_2 0xF04
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#define DEBUG_26 0xF64
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#define DDR_DSR2 0xB24
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#define DDR_CNTRLR_2 0x2
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#define COUNT_100 1000
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.globl _soc_sys_warm_reset
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.align 12
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func _soc_sys_warm_reset
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mov x3, xzr
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b touch_line0
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start_line0:
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mov x3, #1
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mov x2, #NUM_OF_DDRC
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ldr x1, =NXP_DDR_ADDR
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1:
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ldr w0, [x1, #SDRAM_CFG]
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orr w0, w0, #SDRAM_CFG_MEM_HLT
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str w0, [x1, #SDRAM_CFG]
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2:
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ldr w0, [x1, #DEBUG_2]
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and w0, w0, #DDR_DBG_2_MEM_IDLE
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cbz w0, 2b
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ldr w0, [x1, #DEBUG_26]
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orr w0, w0, #DDR_DEBUG_26_BIT_12
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orr w0, w0, #DDR_DEBUG_26_BIT_13
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orr w0, w0, #DDR_DEBUG_26_BIT_14
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touch_line0:
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cbz x3, touch_line1
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orr w0, w0, #DDR_DEBUG_26_BIT_15
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orr w0, w0, #DDR_DEBUG_26_BIT_16
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str w0, [x1, #DEBUG_26]
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ldr w0, [x1, #SDRAM_CFG_2]
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orr w0, w0, #SDRAM_CFG2_FRC_SR
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str w0, [x1, #SDRAM_CFG_2]
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3:
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ldr w0, [x1, #DDR_DSR2]
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orr w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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str w0, [x1, #DDR_DSR2]
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ldr w0, [x1, #DDR_DSR2]
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and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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cbnz w0, 3b
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ldr w0, [x1, #SDRAM_INTERVAL]
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and w0, w0, #SDRAM_INTERVAL_REFINT_CLEAR
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str w0, [x1, #SDRAM_INTERVAL]
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touch_line1:
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cbz x3, touch_line2
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ldr w0, [x1, #SDRAM_MD_CNTL]
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orr w0, w0, #MD_CNTL_CKE(1)
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orr w0, w0, #MD_CNTL_MD_EN
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str w0, [x1, #SDRAM_MD_CNTL]
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ldr w0, [x1, #TIMING_CFG_10]
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orr w0, w0, #DDR_TIMING_CFG_10_T_STAB
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str w0, [x1, #TIMING_CFG_10]
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ldr w0, [x1, #SDRAM_CFG_2]
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and w0, w0, #SDRAM_CFG2_FRC_SR_CLEAR
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str w0, [x1, #SDRAM_CFG_2]
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4:
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ldr w0, [x1, #DDR_DSR2]
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and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
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cbz w0, 4b
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nop
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touch_line2:
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cbz x3, touch_line3
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ldr w0, [x1, #DEBUG_26]
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orr w0, w0, #DDR_DEBUG_26_BIT_25
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and w0, w0, #DDR_DEBUG_26_BIT_24_CLEAR
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str w0, [x1, #DEBUG_26]
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cmp x2, #DDR_CNTRLR_2
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b.ne 5f
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ldr x1, =NXP_DDR2_ADDR
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mov x2, xzr
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b 1b
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5:
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mov x5, xzr
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6:
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add x5, x5, #1
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cmp x5, #COUNT_100
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b.ne 6b
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nop
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touch_line3:
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cbz x3, touch_line4
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#ifdef NXP_COINED_BB
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ldr x1, =NXP_SNVS_ADDR
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ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
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/* On Warm Boot is enabled, then zeroth bit
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* of SNVS LP GPR register 0 will used
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* to save the status of warm-reset as a cause.
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*/
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orr w0, w0, #(1 << NXP_LPGPR_ZEROTH_BIT)
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/* write back */
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str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line4:
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cbz x3, touch_line6
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#elif !(ERLY_WRM_RST_FLG_FLSH_UPDT)
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ldr x1, =NXP_FLEXSPI_ADDR
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ldr w0, [x1, #FSPI_IPCMD]
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orr w0, w0, #FSPI_IPCMD_TRG_MASK
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str w0, [x1, #FSPI_IPCMD]
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7:
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ldr w0, [x1, #FSPI_INTR]
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and w0, w0, #FSPI_INTR_IPCMDDONE_MASK
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cmp w0, #0
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b.eq 7b
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ldr w0, [x1, #FSPI_IPTXFCR]
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orr w0, w0, #FSPI_IPTXFCR_CLR
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str w0, [x1, #FSPI_IPTXFCR]
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ldr w0, [x1, #FSPI_INTR]
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orr w0, w0, #FSPI_INTR_IPCMDDONE_MASK
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str w0, [x1, #FSPI_INTR]
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nop
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touch_line4:
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cbz x3, touch_line5
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/* flexspi driver has an api
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* is_flash_busy().
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* Impelementation of the api will not
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* fit-in in 1 cache line.
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* instead a nop-cycles are introduced to
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* simulate the wait time for flash write
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* completion.
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*
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* Note: This wait time varies from flash to flash.
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*/
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mov x0, #FLASH_WR_COMP_WAIT_BY_NOP_COUNT
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8:
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sub x0, x0, #1
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nop
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cmp x0, #0
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b.ne 8b
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line5:
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cbz x3, touch_line6
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#endif
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ldr x2, =NXP_RST_ADDR
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/* clear the RST_REQ_MSK and SW_RST_REQ */
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mov w0, #0x00000000
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str w0, [x2, #RSTCNTL_OFFSET]
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/* initiate the sw reset request */
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mov w0, #SW_RST_REQ_INIT
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str w0, [x2, #RSTCNTL_OFFSET]
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/* In case this address range is mapped as cacheable,
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* flush the write out of the dcaches.
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*/
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add x2, x2, #RSTCNTL_OFFSET
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dc cvac, x2
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dsb st
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isb
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/* Function does not return */
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b .
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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touch_line6:
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cbz x3, start_line0
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endfunc _soc_sys_warm_reset
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