355 lines
8.8 KiB
C
355 lines
8.8 KiB
C
/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <common/debug.h>
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#include <ddr.h>
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#include <lib/utils.h>
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#include <load_img.h>
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#include "plat_common.h"
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#include <platform_def.h>
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#ifdef CONFIG_STATIC_DDR
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const struct ddr_cfg_regs static_3200 = {
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.cs[0].bnds = U(0x03FFU),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFFAA0018),
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.timing_cfg[1] = U(0x646A8844),
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.timing_cfg[2] = U(0x00058022),
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.timing_cfg[3] = U(0x13622100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x07401400),
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.timing_cfg[7] = U(0x3BB00000),
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.timing_cfg[8] = U(0x0944AC00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010C50),
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.sdram_mode[1] = U(0x00280400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x10240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x30C00000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct ddr_cfg_regs static_2900 = {
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.cs[0].bnds = U(0x03FF),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFF990018),
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.timing_cfg[1] = U(0x4F4A4844),
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.timing_cfg[2] = U(0x0005601F),
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.timing_cfg[3] = U(0x125F2100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x07401400),
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.timing_cfg[7] = U(0x3AA00000),
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.timing_cfg[8] = U(0x09449B00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010C50),
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.sdram_mode[1] = U(0x00280400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x10240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x2C2E0000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct ddr_cfg_regs static_2600 = {
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.cs[0].bnds = U(0x03FF),
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.cs[1].bnds = U(0x03FF),
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.cs[0].config = U(0x80050422),
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.cs[1].config = U(0x80000422),
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.cs[2].bnds = U(0x00),
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.cs[3].bnds = U(0x00),
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.cs[2].config = U(0x00),
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.cs[3].config = U(0x00),
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.timing_cfg[0] = U(0xFF880018),
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.timing_cfg[1] = U(0x2A24F444),
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.timing_cfg[2] = U(0x007141DC),
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.timing_cfg[3] = U(0x125B2100),
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.timing_cfg[4] = U(0x02),
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.timing_cfg[5] = U(0x06401400),
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.timing_cfg[7] = U(0x28800000),
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.timing_cfg[8] = U(0x07338A00),
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.sdram_cfg[0] = U(0x65044008),
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.sdram_cfg[1] = U(0x00401011),
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.sdram_cfg[2] = U(0x00),
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.sdram_mode[0] = U(0x06010A70),
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.sdram_mode[1] = U(0x00200400),
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.sdram_mode[2] = U(0x00),
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.sdram_mode[3] = U(0x00),
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.sdram_mode[4] = U(0x00),
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.sdram_mode[5] = U(0x00),
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.sdram_mode[6] = U(0x00),
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.sdram_mode[7] = U(0x00),
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.sdram_mode[8] = U(0x0500),
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.sdram_mode[9] = U(0x0C240000),
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.sdram_mode[10] = U(0x00),
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.sdram_mode[11] = U(0x00),
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.sdram_mode[12] = U(0x00),
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.sdram_mode[13] = U(0x00),
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.sdram_mode[14] = U(0x00),
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.sdram_mode[15] = U(0x00),
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.md_cntl = U(0x00),
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.interval = U(0x279C0000),
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.data_init = U(0xDEADBEEF),
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.init_addr = U(0x00),
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.zq_cntl = U(0x8A090705),
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.sdram_rcw[0] = U(0x00),
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.sdram_rcw[1] = U(0x00),
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.sdram_rcw[2] = U(0x00),
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.sdram_rcw[3] = U(0x00),
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.sdram_rcw[4] = U(0x00),
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.sdram_rcw[5] = U(0x00),
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.err_disable = U(0x00),
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.err_int_en = U(0x00),
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};
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const struct dimm_params static_dimm = {
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.rdimm = 0U,
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.primary_sdram_width = 64U,
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.ec_sdram_width = 8U,
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.n_ranks = 2U,
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.device_width = 8U,
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.mirrored_dimm = 1U,
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};
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/* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */
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unsigned long long board_static_ddr(struct ddr_info *priv)
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{
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memcpy(&priv->ddr_reg, &static_2900, sizeof(static_2900));
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memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm));
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priv->conf.cs_on_dimm[0] = 0x3;
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ddr_board_options(priv);
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compute_ddr_phy(priv);
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return ULL(0x400000000);
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}
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#elif defined(CONFIG_DDR_NODIMM)
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/*
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* Sample code to bypass reading SPD. This is a sample, not recommended
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* for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1.
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*/
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struct dimm_params ddr_raw_timing = {
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.n_ranks = 2U,
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.rank_density = U(0x200000000),
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.capacity = U(0x400000000),
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.primary_sdram_width = 64U,
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.ec_sdram_width = 8U,
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.device_width = 8U,
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.die_density = U(0x5),
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.rdimm = 0U,
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.mirrored_dimm = 1U,
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.n_row_addr = 16U,
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.n_col_addr = 10U,
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.bank_addr_bits = 0U,
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.bank_group_bits = 2U,
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.edc_config = 2U,
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.burst_lengths_bitmask = U(0x0c),
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.tckmin_x_ps = 625,
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.tckmax_ps = 1600,
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.caslat_x = U(0x15FFFC00),
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.taa_ps = 13750,
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.trcd_ps = 13750,
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.trp_ps = 13750,
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.tras_ps = 32000,
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.trc_ps = 457500,
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.twr_ps = 15000,
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.trfc1_ps = 350000,
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.trfc2_ps = 260000,
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.trfc4_ps = 160000,
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.tfaw_ps = 21000,
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.trrds_ps = 2500,
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.trrdl_ps = 4900,
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.tccdl_ps = 5000,
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.refresh_rate_ps = 7800000U,
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};
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int ddr_get_ddr_params(struct dimm_params *pdimm,
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struct ddr_conf *conf)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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conf->dimm_in_use[0] = 1; /* Modify accordingly */
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memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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/* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
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return 0x5;
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}
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#endif /* CONFIG_DDR_NODIMM */
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int ddr_board_options(struct ddr_info *priv)
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{
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struct memctl_opt *popts = &priv->opt;
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const struct ddr_conf *conf = &priv->conf;
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popts->vref_dimm = U(0x19); /* range 1, 83.4% */
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popts->rtt_override = 1U;
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popts->rtt_override_value = 0x5U; /* RTT being used as 60 ohm */
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popts->rtt_park = 120U;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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popts->trwt_override = 1U;
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popts->bstopre = 0U; /* auto precharge */
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popts->addr_hash = 1;
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/* Set ODT impedance on PHY side */
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switch (conf->cs_on_dimm[1]) {
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case 0xc: /* Two slots dual rank */
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case 0x4: /* Two slots single rank, not valid for interleaving */
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popts->trwt = U(0xf);
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popts->twrt = U(0x7);
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popts->trrt = U(0x7);
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popts->twwt = U(0x7);
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popts->vref_phy = U(0x6B); /* 83.6% */
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popts->odt = 60U;
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popts->phy_tx_impedance = 28U;
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break;
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case 0: /* Ont slot used */
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default:
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popts->trwt = U(0x3);
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popts->twrt = U(0x3);
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popts->trrt = U(0x3);
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popts->twwt = U(0x3);
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popts->vref_phy = U(0x5D); /* 72% */
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popts->odt = 60U;
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popts->phy_tx_impedance = 28U;
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break;
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}
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return 0;
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}
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#ifdef NXP_WARM_BOOT
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long long init_ddr(uint32_t wrm_bt_flg)
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#else
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long long init_ddr(void)
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#endif
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{
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int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 };
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struct ddr_info info;
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struct sysinfo sys;
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long long dram_size;
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zeromem(&sys, sizeof(sys));
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if (get_clocks(&sys) != 0) {
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ERROR("System clocks are not set\n");
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panic();
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}
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debug("platform clock %lu\n", sys.freq_platform);
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debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
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debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
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zeromem(&info, sizeof(info));
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/* Set two DDRC. Unused DDRC will be removed automatically. */
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info.num_ctlrs = NUM_OF_DDRC;
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info.spd_addr = spd_addr;
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info.ddr[0] = (void *)NXP_DDR_ADDR;
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info.ddr[1] = (void *)NXP_DDR2_ADDR;
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info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
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info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
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info.clk = get_ddr_freq(&sys, 0);
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info.img_loadr = load_img;
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info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
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if (info.clk == 0) {
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info.clk = get_ddr_freq(&sys, 1);
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}
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info.dimm_on_ctlr = DDRC_NUM_DIMM;
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info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
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#ifdef NXP_WARM_BOOT
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if (wrm_bt_flg != 0) {
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info.warm_boot_flag = DDR_WARM_BOOT;
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} else {
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info.warm_boot_flag = DDR_COLD_BOOT;
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}
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#endif
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dram_size = dram_init(&info
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#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
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, NXP_CCN_HN_F_0_ADDR
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#endif
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);
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if (dram_size < 0) {
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ERROR("DDR init failed.\n");
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}
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return dram_size;
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}
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