195 lines
6.7 KiB
C
195 lines
6.7 KiB
C
/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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/* Enable the dynamic translation tables library. */
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#define PLAT_XLAT_TABLES_DYNAMIC 1
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#include <common_def.h>
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#include <qti_board_def.h>
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#include <qtiseclib_defs_plat.h>
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/*
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* MPIDR_PRIMARY_CPU
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* You just need to have the correct core_affinity_val i.e. [7:0]
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* and cluster_affinity_val i.e. [15:8]
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* the other bits will be ignored
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*/
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/*----------------------------------------------------------------------------*/
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#define MPIDR_PRIMARY_CPU 0x0000
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/*----------------------------------------------------------------------------*/
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#define QTI_PWR_LVL0 MPIDR_AFFLVL0
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#define QTI_PWR_LVL1 MPIDR_AFFLVL1
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#define QTI_PWR_LVL2 MPIDR_AFFLVL2
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#define QTI_PWR_LVL3 MPIDR_AFFLVL3
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/*
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* Macros for local power states encoded by State-ID field
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* within the power-state parameter.
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*/
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/* Local power state for power domains in Run state. */
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#define QTI_LOCAL_STATE_RUN 0
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/*
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* Local power state for clock-gating. Valid only for CPU and not cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_STB 1
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/*
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* Local power state for retention. Valid for CPU and cluster power
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* domains
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*/
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#define QTI_LOCAL_STATE_RET 2
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/*
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* Local power state for OFF/power down. Valid for CPU, cluster, RSC and PDC
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* power domains
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*/
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#define QTI_LOCAL_STATE_OFF 3
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/*
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* Local power state for DEEPOFF/power rail down. Valid for CPU, cluster and RSC
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* power domains
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*/
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#define QTI_LOCAL_STATE_DEEPOFF 4
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/*
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* This macro defines the deepest retention state possible. A higher state
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* id will represent an invalid or a power down state.
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*/
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#define PLAT_MAX_RET_STATE QTI_LOCAL_STATE_RET
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/*
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* This macro defines the deepest power down states possible. Any state ID
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* higher than this is invalid.
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*/
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#define PLAT_MAX_OFF_STATE QTI_LOCAL_STATE_DEEPOFF
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/******************************************************************************
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* Required platform porting definitions common to all ARM standard platforms
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*****************************************************************************/
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/*
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* Platform specific page table and MMU setup constants.
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*/
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#define MAX_MMAP_REGIONS (PLAT_QTI_MMAP_ENTRIES)
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36)
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#define ARM_CACHE_WRITEBACK_SHIFT 6
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/*
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* Some data must be aligned on the biggest cache line size in the platform.
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* This is known only to the platform as it might have a combination of
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* integrated and external caches.
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*/
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#define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT)
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/*
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* One cache line needed for bakery locks on ARM platforms
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*/
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#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
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/*----------------------------------------------------------------------------*/
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/* PSCI power domain topology definitions */
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/*----------------------------------------------------------------------------*/
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/* One domain each to represent RSC and PDC level */
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#define PLAT_PDC_COUNT 1
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#define PLAT_RSC_COUNT 1
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/* There is one top-level FCM cluster */
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#define PLAT_CLUSTER_COUNT 1
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/* No. of cores in the FCM cluster */
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#define PLAT_CLUSTER0_CORE_COUNT 8
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#define PLATFORM_CORE_COUNT (PLAT_CLUSTER0_CORE_COUNT)
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#define PLAT_NUM_PWR_DOMAINS (PLAT_PDC_COUNT +\
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PLAT_RSC_COUNT +\
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PLAT_CLUSTER_COUNT +\
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PLATFORM_CORE_COUNT)
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#define PLAT_MAX_PWR_LVL 3
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/*****************************************************************************/
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/* Memory mapped Generic timer interfaces */
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/*****************************************************************************/
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/*----------------------------------------------------------------------------*/
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/* GIC-600 constants */
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/*----------------------------------------------------------------------------*/
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#define BASE_GICD_BASE 0x17A00000
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#define BASE_GICR_BASE 0x17A60000
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#define BASE_GICC_BASE 0x0
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#define BASE_GICH_BASE 0x0
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#define BASE_GICV_BASE 0x0
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#define QTI_GICD_BASE BASE_GICD_BASE
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#define QTI_GICR_BASE BASE_GICR_BASE
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#define QTI_GICC_BASE BASE_GICC_BASE
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/*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------*/
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/* UART related constants. */
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/*----------------------------------------------------------------------------*/
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/* BASE ADDRESS OF DIFFERENT REGISTER SPACES IN HW */
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#define GENI4_CFG 0x0
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#define GENI4_IMAGE_REGS 0x100
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#define GENI4_DATA 0x600
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/* COMMON STATUS/CONFIGURATION REGISTERS AND MASKS */
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#define GENI_STATUS_REG (GENI4_CFG + 0x00000040)
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#define GENI_STATUS_M_GENI_CMD_ACTIVE_MASK (0x1)
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#define UART_TX_TRANS_LEN_REG (GENI4_IMAGE_REGS + 0x00000170)
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/* MASTER/TX ENGINE REGISTERS */
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#define GENI_M_CMD0_REG (GENI4_DATA + 0x00000000)
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/* FIFO, STATUS REGISTERS AND MASKS */
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#define GENI_TX_FIFOn_REG (GENI4_DATA + 0x00000100)
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#define GENI_M_CMD_TX (0x08000000)
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/*----------------------------------------------------------------------------*/
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/* Device address space for mapping. Excluding starting 4K */
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/*----------------------------------------------------------------------------*/
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#define QTI_DEVICE_BASE 0x1000
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#define QTI_DEVICE_SIZE (0x80000000 - QTI_DEVICE_BASE)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL31 at DDR as per memory map. BL31_BASE is calculated using the
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* current BL31 debug size plus a little space for growth.
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*/
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/*----------------------------------------------------------------------------*/
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/* AOSS registers */
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/*----------------------------------------------------------------------------*/
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#define QTI_PS_HOLD_REG 0x0C264000
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/*----------------------------------------------------------------------------*/
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/* AOP CMD DB address space for mapping */
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/*----------------------------------------------------------------------------*/
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#define QTI_AOP_CMD_DB_BASE 0x80820000
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#define QTI_AOP_CMD_DB_SIZE 0x00020000
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/*----------------------------------------------------------------------------*/
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/* SOC hw version register */
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/*----------------------------------------------------------------------------*/
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#define QTI_SOC_VERSION U(0x7180)
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#define QTI_SOC_VERSION_MASK U(0xFFFF)
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#define QTI_SOC_REVISION_REG 0x1FC8000
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#define QTI_SOC_REVISION_MASK U(0xFFFF)
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/*----------------------------------------------------------------------------*/
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#endif /* PLATFORM_DEF_H */
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