356 lines
18 KiB
ArmAsm
356 lines
18 KiB
ArmAsm
@/*****************************************************************************
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@*
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@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
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@*
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@* Licensed under the Apache License, Version 2.0 (the "License");
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@* you may not use this file except in compliance with the License.
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@* You may obtain a copy of the License at:
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@*
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@* http://www.apache.org/licenses/LICENSE-2.0
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@*
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@* Unless required by applicable law or agreed to in writing, software
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@* distributed under the License is distributed on an "AS IS" BASIS,
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@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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@* See the License for the specific language governing permissions and
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@* limitations under the License.
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@*
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@*****************************************************************************/
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@/**
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@*******************************************************************************
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@* ,:file
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@* ihevc_sao_edge_offset_class0.s
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@*
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@* ,:brief
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@* Contains function definitions for inter prediction interpolation.
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@* Functions are coded using NEON intrinsics and can be compiled using@ ARM
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@* RVCT
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@*
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@* ,:author
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@* Parthiban V
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@*
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@* ,:par List of Functions:
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@*
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@*
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@* ,:remarks
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@* None
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@*
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@*******************************************************************************
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@*/
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@void ihevc_sao_edge_offset_class0(UWORD8 *pu1_src,
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@ WORD32 src_strd,
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@ UWORD8 *pu1_src_left,
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@ UWORD8 *pu1_src_top,
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@ UWORD8 *pu1_src_top_left,
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@ UWORD8 *pu1_src_top_right,
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@ UWORD8 *pu1_src_bot_left,
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@ UWORD8 *pu1_avail,
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@ WORD8 *pi1_sao_offset,
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@ WORD32 wd,
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@ WORD32 ht)
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@
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@**************Variables Vs Registers*****************************************
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@r0 => *pu1_src
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@r1 => src_strd
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@r2 => *pu1_src_left
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@r3 => *pu1_src_top
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@r4 => *pu1_src_top_left
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@r7 => *pu1_avail
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@r8 => *pi1_sao_offset
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@r9 => wd
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@r10=> ht
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.equ pu1_src_top_left_offset, 104
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.equ pu1_src_top_right_offset, 108
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.equ pu1_src_bot_left_offset, 112
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.equ pu1_avail_offset, 116
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.equ pi1_sao_offset, 120
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.equ wd_offset, 124
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.equ ht_offset, 128
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.text
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.p2align 2
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.extern gi1_table_edge_idx
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.globl ihevc_sao_edge_offset_class0_a9q
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gi1_table_edge_idx_addr:
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.long gi1_table_edge_idx - ulbl1 - 8
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ihevc_sao_edge_offset_class0_a9q:
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STMFD sp!, {r4-r12, r14} @stack stores the values of the arguments
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vpush {d8 - d15}
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LDR r9,[sp,#wd_offset] @Loads wd
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LDR r4,[sp,#pu1_src_top_left_offset] @Loads pu1_src_top_left
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VMOV.I8 Q1,#2 @const_2 = vdupq_n_s8(2)
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ADD r11,r3,r9 @pu1_src_top[wd]
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LDR r10,[sp,#ht_offset] @Loads ht
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VMOV.I16 Q2,#0 @const_min_clip = vdupq_n_s16(0)
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LDRB r12,[r11,#-1] @pu1_src_top[wd - 1]
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LDR r7,[sp,#pu1_avail_offset] @Loads pu1_avail
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VMOV.I16 Q3,#255 @const_max_clip = vdupq_n_u16((1 << bit_depth) - 1)
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LDR r14, gi1_table_edge_idx_addr @table pointer
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ulbl1:
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add r14,r14,pc
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LDR r8,[sp,#pi1_sao_offset] @Loads pi1_sao_offset
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VMOV.S8 Q4,#0xFF @au1_mask = vdupq_n_s8(-1)
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STRB r12,[r4] @*pu1_src_top_left = pu1_src_top[wd - 1]
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MOV r6,r0 @pu1_src_org
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VLD1.8 D10,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
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SUB r4,r10,#1 @(ht - 1)
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MOV r12,r9 @Move wd to r12 for loop count
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VLD1.8 D11,[r8] @offset_tbl = vld1_s8(pi1_sao_offset)
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MUL r4,r4,r1 @(ht - 1) * src_strd
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ADD r4,r4,r0 @pu1_src[(ht - 1) * src_strd]
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SRC_TOP_LOOP: @wd is always multiple of 8
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VLD1.8 D0,[r4]! @Load pu1_src[(ht - 1) * src_strd + col]
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SUBS r12,r12,#8 @Decrement the loop counter by 8
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VST1.8 D0,[r3]! @Store to pu1_src_top[col]
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BNE SRC_TOP_LOOP
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ADD r6,r6,#15 @pu1_src_org[16 - 1]
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CMP r9,#16 @Compare wd with 16
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MOV r3,r2 @pu1_src_left backup to reload later
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BLT WIDTH_RESIDUE @If not jump to WIDTH_RESIDUE where loop is unrolled for 8 case
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MOV r8,r9 @move wd to r8 for loop count
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WIDTH_LOOP_16:
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CMP r8,r9 @if(col == wd)
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BNE AU1_MASK_FF @jump to else part
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LDRB r12,[r7] @pu1_avail[0]
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VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
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B SKIP_AU1_MASK_FF @Skip the else part
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AU1_MASK_FF:
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MOV r12,#0xFF @move -1 to r12
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VMOV.8 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
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SKIP_AU1_MASK_FF:
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CMP r8,#16 @If col == 16
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BNE SKIP_MASKING_IF_NOT16 @If not skip masking
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LDRB r12,[r7,#1] @pu1_avail[1]
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VMOV.8 D9[7],r12 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
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SKIP_MASKING_IF_NOT16:
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MOV r12,r0 @pu1_src_cpy = pu1_src
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MOV r4,r10 @move ht to r4 for loop count
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PU1_SRC_LOOP:
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LDRB r11,[r2] @load pu1_src_left since ht - row =0 when it comes first pu1_src_left is incremented later
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VLD1.8 D12,[r12]! @pu1_cur_row = vld1q_u8(pu1_src_cpy)
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VLD1.8 D13,[r12], r1 @pu1_cur_row = vld1q_u8(pu1_src_cpy)
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SUB r12,#8
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SUB r5,r9,r8 @wd - col
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SUB r14,r10,r4 @ht - row
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VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
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MUL r14,r14,r1 @(ht - row) * src_strd
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VLD1.8 D26,[r12]! @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
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VLD1.8 D27,[r12] @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
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SUB r12,#8
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VEXT.8 Q7,Q7,Q6,#15 @pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
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ADD r5,r14,r5 @(ht - row) * src_strd + (wd - col)
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LDRB r11,[r2, #1] @II Iteration load pu1_src_left since ht - row + 1 =1
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VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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LDRB r14,[r6,r5] @pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - col)]
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SUB r4,r4,#1
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VMOV.8 D29[7],r11 @II Iteration vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
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VCLT.U8 Q9,Q6,Q7 @vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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SUB r12,r12,r1 @Decrement the pu1_src pointer by src_strd
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VSUB.I8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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STRB r14,[r2],#1 @pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
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LDRB r11,[r12,#16] @pu1_src_cpy[16]
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VEXT.8 Q14,Q14,Q13,#15 @II Iteration pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
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SUB r5,r9,r8 @II wd - col
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ADD r12,r12,r1 @Increment the pu1_src pointer by src_strd
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VMOV.8 D14[0],r11 @pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[16], pu1_cur_row_tmp, 0)
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VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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LDRB r11,[r12,#16] @II pu1_src_cpy[16]
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VEXT.8 Q7,Q6,Q7,#1 @pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
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SUB r14,r10,r4 @II ht - row
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VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VMOV.8 D28[0],r11 @II pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[16], pu1_cur_row_tmp, 0)
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SUB r12,r12,r1 @Decrement the pu1_src pointer by src_strd
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MUL r14,r14,r1 @II (ht - row) * src_strd
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VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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ADD r5,r14,r5 @II (ht - row) * src_strd + (wd - col)
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VCLT.U8 Q9,Q6,Q7 @vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VEXT.8 Q14,Q13,Q14,#1 @II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
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LDRB r14,[r6,r5] @II pu1_src_org[(ht - row) * src_strd + 16 - 1 + (wd - col)]
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VSUB.I8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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SUBS r4,r4,#1 @Decrement row by 1
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VADD.I8 Q7,Q1,Q10 @edge_idx = vaddq_s8(const_2, sign_left)
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STRB r14,[r2],#1 @II pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
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VADD.I8 Q7,Q7,Q11 @edge_idx = vaddq_s8(edge_idx, sign_right)
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VMOVL.U8 Q9,D12 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(vget_low_u8(pu1_cur_row)))
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VSUB.I8 Q10,Q0,Q15 @II sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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VTBL.8 D14,{D10},D14 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
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VCGT.U8 Q15,Q13,Q14 @II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VCLT.U8 Q0,Q13,Q14 @II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VTBL.8 D15,{D10},D15 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
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VSUB.I8 Q11,Q0,Q15 @II sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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VAND Q7,Q7,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
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VTBL.8 D16,{D11},D14 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
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VMOVL.U8 Q0,D26 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(vget_low_u8(pu1_cur_row)))
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VADD.I8 Q14,Q1,Q10 @II edge_idx = vaddq_s8(const_2, sign_left)
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VADD.I8 Q14,Q14,Q11 @II edge_idx = vaddq_s8(edge_idx, sign_right)
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VADDW.S8 Q9,Q9,D16 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0], offset)
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VTBL.8 D28,{D10},D28 @II vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
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VMAX.S16 Q9,Q9,Q2 @pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val[0], const_min_clip)
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VTBL.8 D29,{D10},D29 @II vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
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VMIN.U16 Q9,Q9,Q3 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
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VAND Q14,Q14,Q4 @II edge_idx = vandq_s8(edge_idx, au1_mask)
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VTBL.8 D17,{D11},D15 @offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
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VMOVL.U8 Q7,D13 @pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_u8(vget_high_u8(pu1_cur_row)))
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VTBL.8 D30,{D11},D28 @II offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
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VADDW.S8 Q7,Q7,D17 @pi2_tmp_cur_row.val[1] = vaddw_s8(pi2_tmp_cur_row.val[1], offset)
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VMAX.S16 Q7,Q7,Q2 @pi2_tmp_cur_row.val[1] = vmaxq_s16(pi2_tmp_cur_row.val[1], const_min_clip)
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VTBL.8 D31,{D11},D29 @II offset = vtbl1_s8(offset_tbl, vget_high_s8(edge_idx))
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VMIN.U16 Q7,Q7,Q3 @pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
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VMOVN.I16 D18,Q9 @vmovn_s16(pi2_tmp_cur_row.val[0])
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VADDW.S8 Q0,Q0,D30 @II pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0], offset)
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VMOVN.I16 D19,Q7 @vmovn_s16(pi2_tmp_cur_row.val[1])
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VMAX.S16 Q0,Q0,Q2 @II pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val[0], const_min_clip)
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VMOVL.U8 Q14,D27 @II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_u8(vget_high_u8(pu1_cur_row)))
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VMIN.U16 Q0,Q0,Q3 @II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
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VMOVN.I16 D0,Q0 @II vmovn_s16(pi2_tmp_cur_row.val[0])
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VADDW.S8 Q14,Q14,D31 @II pi2_tmp_cur_row.val[1] = vaddw_s8(pi2_tmp_cur_row.val[1], offset)
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VMAX.S16 Q14,Q14,Q2 @II pi2_tmp_cur_row.val[1] = vmaxq_s16(pi2_tmp_cur_row.val[1], const_min_clip)
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VST1.8 {D18,D19},[r12],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
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VMIN.U16 Q14,Q14,Q3 @II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[1]), const_max_clip))
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VMOVN.I16 D1,Q14 @II vmovn_s16(pi2_tmp_cur_row.val[1])
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VST1.8 {D0,D1},[r12],r1 @II vst1q_u8(pu1_src_cpy, pu1_cur_row)
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BNE PU1_SRC_LOOP @If not equal jump to the inner loop
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ADD r0,r0,#16 @pu1_src += 16
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SUBS r8,r8,#16 @Decrement column by 16
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CMP r8,#8 @Check whether residue remains
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MOV r2,r3 @Reload pu1_src_left
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BEQ WIDTH_RESIDUE @If residue remains jump to residue loop
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BGT WIDTH_LOOP_16 @If not equal jump to width_loop
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BLT END_LOOPS @Jump to end function
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WIDTH_RESIDUE:
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SUB r6,r6,#15
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AND r8,r9,#0xF @wd_rem = wd & 0xF
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CMP r8,#0 @Residue check
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BEQ END_LOOPS @No Residue jump to end function
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CMP r8,r9 @if(wd_rem == wd)
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BNE AU1_MASK_FF_RESIDUE @jump to else part
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LDRB r12,[r7] @pu1_avail[0]
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VMOV.8 D8[0],r12 @vsetq_lane_s8(pu1_avail[0], au1_mask, 0)
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B SKIP_AU1_MASK_FF_RESIDUE @Skip the else part
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AU1_MASK_FF_RESIDUE:
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MOV r12,#0xFF @move -s to r12
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VMOV.8 D8[0],r12 @au1_mask = vsetq_lane_s8(-1, au1_mask, 0)
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SKIP_AU1_MASK_FF_RESIDUE:
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LDRB r11,[r7,#1] @pu1_avail[1]
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SUB r5,r9,#1 @wd - 1
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MOV r4,r10 @move ht to r4 for loop count
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VMOV.8 D8[7],r11 @au1_mask = vsetq_lane_s8(pu1_avail[1], au1_mask, 15)
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MOV r12,r0 @pu1_src_cpy = pu1_src
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PU1_SRC_LOOP_RESIDUE:
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VLD1.8 D12,[r12]! @pu1_cur_row = vld1q_u8(pu1_src_cpy)
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VLD1.8 D13,[r12] @pu1_cur_row = vld1q_u8(pu1_src_cpy)
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SUB r12,#8
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LDRB r11,[r2] @load pu1_src_left
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VMOV.8 D15[7],r11 @vsetq_lane_u8(pu1_src_left[ht - row], pu1_cur_row_tmp, 15)
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VEXT.8 Q7,Q7,Q6,#15 @pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
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VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VCLT.U8 Q9,Q6,Q7 @vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VSUB.I8 Q10,Q9,Q8 @sign_left = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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LDRB r11,[r12,#16] @pu1_src_cpy[16]
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VMOV.8 D14[0],r11 @pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[16], pu1_cur_row_tmp, 0)
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VEXT.8 Q7,Q6,Q7,#1 @pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
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VCGT.U8 Q8,Q6,Q7 @vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VCLT.U8 Q9,Q6,Q7 @vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
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VSUB.I8 Q11,Q9,Q8 @sign_right = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp_gt))
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VADD.I8 Q12,Q1,Q10 @edge_idx = vaddq_s8(const_2, sign_left)
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VADD.I8 Q12,Q12,Q11 @edge_idx = vaddq_s8(edge_idx, sign_right)
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VTBL.8 D24,{D10},D24 @vtbl1_s8(edge_idx_tbl, vget_low_s8(edge_idx))
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VTBL.8 D25,{D10},D25 @vtbl1_s8(edge_idx_tbl, vget_high_s8(edge_idx))
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VAND Q12,Q12,Q4 @edge_idx = vandq_s8(edge_idx, au1_mask)
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VNEG.S8 Q10,Q11 @sign_left = vnegq_s8(sign_right)
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VEXT.8 Q10,Q10,Q11,#15 @sign_left = vextq_s8(sign_left, sign_left, 15)
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VTBL.8 D26,{D11},D24 @offset = vtbl1_s8(offset_tbl, vget_low_s8(edge_idx))
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VMOVL.U8 Q14,D12 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_u8(vget_low_u8(pu1_cur_row)))
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VADDW.S8 Q14,Q14,D26 @pi2_tmp_cur_row.val[0] = vaddw_s8(pi2_tmp_cur_row.val[0], offset)
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VMAX.S16 Q14,Q14,Q2 @pi2_tmp_cur_row.val[0] = vmaxq_s16(pi2_tmp_cur_row.val[0], const_min_clip)
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VMIN.U16 Q14,Q14,Q3 @pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vminq_u16(vreinterpretq_u16_s16(pi2_tmp_cur_row.val[0]), const_max_clip))
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VMOVN.I16 D28,Q14 @vmovn_s16(pi2_tmp_cur_row.val[0])
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SUB r14,r10,r4 @ht - row
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MUL r14,r14,r1 @(ht - row) * src_strd
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ADD r11,r14,r5 @(ht - row) * src_strd + (wd - 1)
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LDRB r14,[r6, r11] @pu1_src_org[(ht - row) * src_strd + (wd - 1)]
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STRB r14,[r2],#1 @pu1_src_left[(ht - row)] = au1_src_left_tmp[(ht - row)]
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VST1.8 {D28},[r12],r1 @vst1q_u8(pu1_src_cpy, pu1_cur_row)
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SUBS r4,r4,#1 @Decrement row by 1
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BNE PU1_SRC_LOOP_RESIDUE @If not equal jump to the pu1_src loop
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END_LOOPS:
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vpop {d8 - d15}
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LDMFD sp!,{r4-r12,r15} @Reload the registers from SP
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