354 lines
10 KiB
C
354 lines
10 KiB
C
/**
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******************************************************************************
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*
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* @file hal_desc.h
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*
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* @brief File containing the definition of HW descriptors.
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*
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* Contains the definition and structures used by HW
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*
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* Copyright (C) RivieraWaves 2011-2019
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*
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******************************************************************************
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*/
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#ifndef _HAL_DESC_H_
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#define _HAL_DESC_H_
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#include "lmac_types.h"
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/* Rate and policy table */
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#define N_CCK 8
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#define N_OFDM 8
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#define N_HT (8 * 2 * 2 * 4)
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#define N_VHT (10 * 4 * 2 * 8)
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#define N_HE_SU (12 * 4 * 3 * 8)
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#define N_HE_MU (12 * 6 * 3 * 8)
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#define N_HE_ER (3 * 3 + 3) //RU242 + RU106
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/* conversion table from NL80211 to MACHW enum */
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extern const int chnl2bw[];
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/* conversion table from MACHW to NL80211 enum */
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extern const int bw2chnl[];
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/* Values for formatModTx */
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#define FORMATMOD_NON_HT 0
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#define FORMATMOD_NON_HT_DUP_OFDM 1
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#define FORMATMOD_HT_MF 2
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#define FORMATMOD_HT_GF 3
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#define FORMATMOD_VHT 4
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#define FORMATMOD_HE_SU 5
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#define FORMATMOD_HE_MU 6
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#define FORMATMOD_HE_ER 7
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#define FORMATMOD_HE_TB 8
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/* Values for navProtFrmEx */
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#define NAV_PROT_NO_PROT_BIT 0
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#define NAV_PROT_SELF_CTS_BIT 1
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#define NAV_PROT_RTS_CTS_BIT 2
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#define NAV_PROT_RTS_CTS_WITH_QAP_BIT 3
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#define NAV_PROT_STBC_BIT 4
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/* THD MACCTRLINFO2 fields, used in struct umacdesc umac.flags */
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/// WhichDescriptor definition - contains aMPDU bit and position value
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/// Offset of WhichDescriptor field in the MAC CONTROL INFO 2 word
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#define WHICHDESC_OFT 19
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/// Mask of the WhichDescriptor field
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#define WHICHDESC_MSK (0x07 << WHICHDESC_OFT)
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/// Only 1 THD possible, describing an unfragmented MSDU
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#define WHICHDESC_UNFRAGMENTED_MSDU (0x00 << WHICHDESC_OFT)
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/// THD describing the first MPDU of a fragmented MSDU
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#define WHICHDESC_FRAGMENTED_MSDU_FIRST (0x01 << WHICHDESC_OFT)
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/// THD describing intermediate MPDUs of a fragmented MSDU
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#define WHICHDESC_FRAGMENTED_MSDU_INT (0x02 << WHICHDESC_OFT)
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/// THD describing the last MPDU of a fragmented MSDU
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#define WHICHDESC_FRAGMENTED_MSDU_LAST (0x03 << WHICHDESC_OFT)
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/// THD for extra descriptor starting an AMPDU
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#define WHICHDESC_AMPDU_EXTRA (0x04 << WHICHDESC_OFT)
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/// THD describing the first MPDU of an A-MPDU
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#define WHICHDESC_AMPDU_FIRST (0x05 << WHICHDESC_OFT)
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/// THD describing intermediate MPDUs of an A-MPDU
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#define WHICHDESC_AMPDU_INT (0x06 << WHICHDESC_OFT)
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/// THD describing the last MPDU of an A-MPDU
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#define WHICHDESC_AMPDU_LAST (0x07 << WHICHDESC_OFT)
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/// aMPDU bit offset
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#define AMPDU_OFT 21
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/// aMPDU bit
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#define AMPDU_BIT CO_BIT(AMPDU_OFT)
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union rwnx_mcs_index {
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struct {
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u32 mcs : 3;
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u32 nss : 2;
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} ht;
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struct {
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u32 mcs : 4;
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u32 nss : 3;
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} vht;
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struct {
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u32 mcs : 4;
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u32 nss : 3;
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} he;
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u32 legacy : 7;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union rwnx_rate_ctrl_info {
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struct {
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u32 mcsIndexTx : 7;
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u32 bwTx : 2;
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u32 giAndPreTypeTx : 2;
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u32 formatModTx : 3;
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u32 navProtFrmEx : 3;
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u32 mcsIndexProtTx : 7;
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u32 bwProtTx : 2;
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u32 formatModProtTx : 3;
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u32 nRetry : 3;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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struct rwnx_power_ctrl_info {
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u32 txPwrLevelPT : 8;
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u32 txPwrLevelProtPT : 8;
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u32 reserved :16;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union rwnx_pol_phy_ctrl_info_1 {
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struct {
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u32 rsvd1 : 3;
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u32 bfFrmEx : 1;
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u32 numExtnSS : 2;
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u32 fecCoding : 1;
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u32 stbc : 2;
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u32 rsvd2 : 5;
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u32 nTx : 3;
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u32 nTxProt : 3;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union rwnx_pol_phy_ctrl_info_2 {
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struct {
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u32 antennaSet : 8;
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u32 smmIndex : 8;
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u32 beamFormed : 1;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union rwnx_pol_mac_ctrl_info_1 {
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struct {
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u32 keySRamIndex : 10;
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u32 keySRamIndexRA : 10;
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};
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u32 value;
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};
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/* c.f RW-WLAN-nX-MAC-HW-UM */
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union rwnx_pol_mac_ctrl_info_2 {
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struct {
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u32 longRetryLimit : 8;
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u32 shortRetryLimit : 8;
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u32 rtsThreshold : 12;
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};
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u32 value;
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};
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#define POLICY_TABLE_PATTERN 0xBADCAB1E
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struct tx_policy_tbl {
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/* Unique Pattern at the start of Policy Table */
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u32 upatterntx;
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/* PHY Control 1 Information used by MAC HW */
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union rwnx_pol_phy_ctrl_info_1 phyctrlinfo_1;
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/* PHY Control 2 Information used by MAC HW */
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union rwnx_pol_phy_ctrl_info_2 phyctrlinfo_2;
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/* MAC Control 1 Information used by MAC HW */
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union rwnx_pol_mac_ctrl_info_1 macctrlinfo_1;
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/* MAC Control 2 Information used by MAC HW */
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union rwnx_pol_mac_ctrl_info_2 macctrlinfo_2;
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union rwnx_rate_ctrl_info ratectrlinfos[NX_TX_MAX_RATES];
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struct rwnx_power_ctrl_info powerctrlinfos[NX_TX_MAX_RATES];
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};
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#ifdef CONFIG_RWNX_FULLMAC
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/**
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* struct rwnx_hw_txstatus - Bitfield of confirmation status
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*
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* @tx_done: packet has been processed by the firmware.
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* @retry_required: packet has been transmitted but not acknoledged.
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* Driver must repush it.
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* @sw_retry_required: packet has not been transmitted (FW wasn't able to push
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* it when it received it: not active channel ...). Driver must repush it.
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* @acknowledged: packet has been acknowledged by peer
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*/
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union rwnx_hw_txstatus {
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struct {
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u32 tx_done : 1;
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u32 retry_required : 1;
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u32 sw_retry_required : 1;
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u32 acknowledged : 1;
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u32 reserved :28;
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};
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u32 value;
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};
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/**
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* struct tx_cfm_tag - Structure indicating the status and other
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* information about the transmission
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*
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* @pn: PN that was used for the transmission
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* @sn: Sequence number of the packet
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* @timestamp: Timestamp of first transmission of this MPDU
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* @credits: Number of credits to be reallocated for the txq that push this
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* buffer (can be 0 or 1)
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* @ampdu_size: Size of the ampdu in which the frame has been transmitted if
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* this was the last frame of the a-mpdu, and 0 if the frame is not the last
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* frame on a a-mdpu.
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* 1 means that the frame has been transmitted as a singleton.
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* @amsdu_size: Size, in bytes, allowed to create a-msdu.
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* @status: transmission status
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*/
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struct tx_cfm_tag {
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/*
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u16_l pn[4];
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u16_l sn;
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u16_l timestamp;
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*/
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s8_l credits;
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u8_l ampdu_size;
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#ifdef CONFIG_RWNX_SPLIT_TX_BUF
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u16_l amsdu_size;
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#endif
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union rwnx_hw_txstatus status;
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u32_l hostid;
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};
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/**
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* struct rwnx_hw_txhdr - Hardware part of tx header
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*
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* @cfm: Information updated by fw/hardware after sending a frame
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*/
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struct rwnx_hw_txhdr {
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struct tx_cfm_tag cfm;
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};
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#endif /* CONFIG_RWNX_FULLMAC */
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/* Modem */
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#define MDM_PHY_CONFIG_TRIDENT 0
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#define MDM_PHY_CONFIG_ELMA 1
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#define MDM_PHY_CONFIG_KARST 2
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// MODEM features (from reg_mdm_stat.h)
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/// MUMIMOTX field bit
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#define MDM_MUMIMOTX_BIT ((u32)0x80000000)
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/// MUMIMOTX field position
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#define MDM_MUMIMOTX_POS 31
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/// MUMIMORX field bit
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#define MDM_MUMIMORX_BIT ((u32)0x40000000)
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/// MUMIMORX field position
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#define MDM_MUMIMORX_POS 30
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/// BFMER field bit
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#define MDM_BFMER_BIT ((u32)0x20000000)
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/// BFMER field position
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#define MDM_BFMER_POS 29
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/// BFMEE field bit
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#define MDM_BFMEE_BIT ((u32)0x10000000)
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/// BFMEE field position
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#define MDM_BFMEE_POS 28
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/// LDPCDEC field bit
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#define MDM_LDPCDEC_BIT ((u32)0x08000000)
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/// LDPCDEC field position
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#define MDM_LDPCDEC_POS 27
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/// LDPCENC field bit
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#define MDM_LDPCENC_BIT ((u32)0x04000000)
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/// LDPCENC field position
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#define MDM_LDPCENC_POS 26
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/// CHBW field mask
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#define MDM_CHBW_MASK ((u32)0x03000000)
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/// CHBW field LSB position
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#define MDM_CHBW_LSB 24
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/// CHBW field width
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#define MDM_CHBW_WIDTH ((u32)0x00000002)
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/// DSSSCCK field bit
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#define MDM_DSSSCCK_BIT ((u32)0x00800000)
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/// DSSSCCK field position
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#define MDM_DSSSCCK_POS 23
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/// VHT field bit
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#define MDM_VHT_BIT ((u32)0x00400000)
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/// VHT field position
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#define MDM_VHT_POS 22
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/// HE field bit
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#define MDM_HE_BIT ((u32)0x00200000)
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/// HE field position
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#define MDM_HE_POS 21
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/// ESS field bit
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#define MDM_ESS_BIT ((u32)0x00100000)
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/// ESS field position
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#define MDM_ESS_POS 20
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/// RFMODE field mask
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#define MDM_RFMODE_MASK ((u32)0x000F0000)
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/// RFMODE field LSB position
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#define MDM_RFMODE_LSB 16
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/// RFMODE field width
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#define MDM_RFMODE_WIDTH ((u32)0x00000004)
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/// NSTS field mask
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#define MDM_NSTS_MASK ((u32)0x0000F000)
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/// NSTS field LSB position
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#define MDM_NSTS_LSB 12
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/// NSTS field width
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#define MDM_NSTS_WIDTH ((u32)0x00000004)
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/// NSS field mask
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#define MDM_NSS_MASK ((u32)0x00000F00)
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/// NSS field LSB position
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#define MDM_NSS_LSB 8
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/// NSS field width
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#define MDM_NSS_WIDTH ((u32)0x00000004)
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/// NTX field mask
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#define MDM_NTX_MASK ((u32)0x000000F0)
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/// NTX field LSB position
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#define MDM_NTX_LSB 4
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/// NTX field width
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#define MDM_NTX_WIDTH ((u32)0x00000004)
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/// NRX field mask
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#define MDM_NRX_MASK ((u32)0x0000000F)
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/// NRX field LSB position
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#define MDM_NRX_LSB 0
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/// NRX field width
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#define MDM_NRX_WIDTH ((u32)0x00000004)
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#define __MDM_PHYCFG_FROM_VERS(v) (((v) & MDM_RFMODE_MASK) >> MDM_RFMODE_LSB)
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#define RIU_FCU_PRESENT_MASK ((u32)0xFF000000)
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#define RIU_FCU_PRESENT_LSB 24
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#define __RIU_FCU_PRESENT(v) (((v) & RIU_FCU_PRESENT_MASK) >> RIU_FCU_PRESENT_LSB == 5)
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/// AGC load version field mask
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#define RIU_AGC_LOAD_MASK ((u32)0x00C00000)
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/// AGC load version field LSB position
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#define RIU_AGC_LOAD_LSB 22
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#define __RIU_AGCLOAD_FROM_VERS(v) (((v) & RIU_AGC_LOAD_MASK) >> RIU_AGC_LOAD_LSB)
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#define __FPGA_TYPE(v) (((v) & 0xFFFF0000) >> 16)
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#define __MDM_MAJOR_VERSION(v) (((v) & 0xFF000000) >> 24)
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#define __MDM_MINOR_VERSION(v) (((v) & 0x00FF0000) >> 16)
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#define __MDM_VERSION(v) ((__MDM_MAJOR_VERSION(v) + 2) * 10 + __MDM_MINOR_VERSION(v))
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#endif // _HAL_DESC_H_
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