298 lines
8.5 KiB
C
298 lines
8.5 KiB
C
/**
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******************************************************************************
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*
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* @file rwnx_dini.c - Add support for dini platform
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*
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* Copyright (C) RivieraWaves 2012-2019
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*
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******************************************************************************
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*/
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#include "rwnx_dini.h"
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#include "rwnx_defs.h"
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#include "rwnx_irqs.h"
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#include "reg_access.h"
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/* Config FPGA is accessed via bar0 */
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#define CFPGA_DMA0_CTRL_REG 0x02C
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#define CFPGA_DMA1_CTRL_REG 0x04C
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#define CFPGA_DMA2_CTRL_REG 0x06C
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#define CFPGA_UINTR_SRC_REG 0x0E8
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#define CFPGA_UINTR_MASK_REG 0x0EC
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#define CFPGA_BAR4_HIADDR_REG 0x100
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#define CFPGA_BAR4_LOADDR_REG 0x104
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#define CFPGA_BAR4_LOADDR_MASK_REG 0x110
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#define CFPGA_BAR_TOUT 0x120
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#define CFPGA_DMA_CTRL_ENABLE 0x00001400
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#define CFPGA_DMA_CTRL_DISABLE 0x00001000
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#define CFPGA_DMA_CTRL_CLEAR 0x00001800
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#define CFPGA_DMA_CTRL_REREAD_TIME_MASK (BIT(10) - 1)
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#define CFPGA_BAR4_LOADDR_MASK_MAX 0xFF000000
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#define CFPGA_PCIEX_IT 0x00000001
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#define CFPGA_ALL_ITS 0x0000000F
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/* Programmable BAR4 Window start address */
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#define CPU_RAM_WINDOW_HIGH 0x00000000
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#define CPU_RAM_WINDOW_LOW 0x00000000
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#define AHB_BRIDGE_WINDOW_HIGH 0x00000000
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#define AHB_BRIDGE_WINDOW_LOW 0x60000000
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struct rwnx_dini {
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u8 *pci_bar0_vaddr;
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u8 *pci_bar4_vaddr;
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};
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static const u32 mv_cfg_fpga_dma_ctrl_regs[] = {
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CFPGA_DMA0_CTRL_REG,
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CFPGA_DMA1_CTRL_REG,
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CFPGA_DMA2_CTRL_REG
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};
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/* This also clears running transactions */
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static void dini_dma_on(struct rwnx_dini *rwnx_dini)
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{
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int i;
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u32 reread_time;
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volatile void *reg;
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for (i = 0; i < ARRAY_SIZE(mv_cfg_fpga_dma_ctrl_regs); i++) {
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reg = rwnx_dini->pci_bar0_vaddr + mv_cfg_fpga_dma_ctrl_regs[i];
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reread_time = readl(reg) & CFPGA_DMA_CTRL_REREAD_TIME_MASK;
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writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
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writel(CFPGA_DMA_CTRL_ENABLE | reread_time, reg);
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}
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}
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/* This also clears running transactions */
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static void dini_dma_off(struct rwnx_dini *rwnx_dini)
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{
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int i;
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u32 reread_time;
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volatile void *reg;
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for (i = 0; i < ARRAY_SIZE(mv_cfg_fpga_dma_ctrl_regs); i++) {
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reg = rwnx_dini->pci_bar0_vaddr + mv_cfg_fpga_dma_ctrl_regs[i];
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reread_time = readl(reg) & CFPGA_DMA_CTRL_REREAD_TIME_MASK;
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writel(CFPGA_DMA_CTRL_DISABLE | reread_time, reg);
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writel(CFPGA_DMA_CTRL_CLEAR | reread_time, reg);
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}
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}
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/* Configure address range for BAR4.
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* By default BAR4_LOADDR_MASK value is 0xFF000000, then there is no need to
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* change it because the addresses we need to access are covered by this mask
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*/
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static void dini_set_bar4_win(u32 low, u32 high, struct rwnx_dini *rwnx_dini)
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{
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writel(low, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_LOADDR_REG);
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writel(high, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_HIADDR_REG);
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writel(CFPGA_BAR4_LOADDR_MASK_MAX,
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rwnx_dini->pci_bar0_vaddr + CFPGA_BAR4_LOADDR_MASK_REG);
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}
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/**
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* Enable User Interrupts of CFPGA that trigger PCIe IRQs on PCIE_10
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* and request the corresponding IRQ line
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*/
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int rwnx_cfpga_irq_enable(struct rwnx_hw *rwnx_hw)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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unsigned int cfpga_uintr_mask;
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volatile void *reg;
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int ret;
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/* sched_setscheduler on ONESHOT threaded irq handler for BCNs ? */
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ret = request_irq(rwnx_hw->plat->pci_dev->irq, rwnx_irq_hdlr, 0, "rwnx", rwnx_hw);
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if (ret)
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return ret;
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reg = rwnx_dini->pci_bar0_vaddr + CFPGA_UINTR_MASK_REG;
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cfpga_uintr_mask = readl(reg);
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writel(cfpga_uintr_mask | CFPGA_PCIEX_IT, reg);
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return ret;
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}
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/**
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* Disable User Interrupts of CFPGA that trigger PCIe IRQs on PCIE_10
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* and free the corresponding IRQ line
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*/
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int rwnx_cfpga_irq_disable(struct rwnx_hw *rwnx_hw)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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unsigned int cfpga_uintr_mask;
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volatile void *reg;
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reg = rwnx_dini->pci_bar0_vaddr + CFPGA_UINTR_MASK_REG;
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cfpga_uintr_mask = readl(reg);
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writel(cfpga_uintr_mask & ~CFPGA_PCIEX_IT, reg);
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free_irq(rwnx_hw->plat->pci_dev->irq, rwnx_hw);
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return 0;
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}
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static int rwnx_dini_platform_enable(struct rwnx_hw *rwnx_hw)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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#ifdef CONFIG_RWNX_SDM
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writel(0x0000FFFF, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR_TOUT);
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#endif
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dini_dma_on(rwnx_dini);
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return rwnx_cfpga_irq_enable(rwnx_hw);
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}
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static int rwnx_dini_platform_disable(struct rwnx_hw *rwnx_hw)
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{
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struct rwnx_plat *rwnx_plat = rwnx_hw->plat;
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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int ret;
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ret = rwnx_cfpga_irq_disable(rwnx_hw);
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dini_dma_off(rwnx_dini);
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return ret;
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}
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static void rwnx_dini_platform_deinit(struct rwnx_plat *rwnx_plat)
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{
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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pci_disable_device(rwnx_plat->pci_dev);
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iounmap(rwnx_dini->pci_bar0_vaddr);
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iounmap(rwnx_dini->pci_bar4_vaddr);
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pci_release_regions(rwnx_plat->pci_dev);
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kfree(rwnx_plat);
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}
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static u8 *rwnx_dini_get_address(struct rwnx_plat *rwnx_plat, int addr_name,
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unsigned int offset)
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{
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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if (WARN(addr_name >= RWNX_ADDR_MAX, "Invalid address %d", addr_name))
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return NULL;
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if (addr_name == RWNX_ADDR_CPU)
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dini_set_bar4_win(CPU_RAM_WINDOW_LOW, CPU_RAM_WINDOW_HIGH, rwnx_dini);
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else
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dini_set_bar4_win(AHB_BRIDGE_WINDOW_LOW, AHB_BRIDGE_WINDOW_HIGH, rwnx_dini);
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return rwnx_dini->pci_bar4_vaddr + offset;
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}
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static void rwnx_dini_ack_irq(struct rwnx_plat *rwnx_plat)
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{
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struct rwnx_dini *rwnx_dini = (struct rwnx_dini *)rwnx_plat->priv;
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writel(CFPGA_ALL_ITS, rwnx_dini->pci_bar0_vaddr + CFPGA_UINTR_SRC_REG);
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}
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static const u32 rwnx_dini_config_reg[] = {
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NXMAC_DEBUG_PORT_SEL_ADDR,
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SYSCTRL_DIAG_CONF_ADDR,
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RF_V6_DIAGPORT_CONF1_ADDR,
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RF_v6_PHYDIAG_CONF1_ADDR,
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};
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static int rwnx_dini_get_config_reg(struct rwnx_plat *rwnx_plat, const u32 **list)
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{
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if (!list)
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return 0;
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*list = rwnx_dini_config_reg;
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return ARRAY_SIZE(rwnx_dini_config_reg);
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}
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/**
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* rwnx_dini_platform_init - Initialize the DINI platform
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*
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* @pci_dev PCI device
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* @rwnx_plat Pointer on struct rwnx_stat * to be populated
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*
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* @return 0 on success, < 0 otherwise
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*
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* Allocate and initialize a rwnx_plat structure for the dini platform.
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*/
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int rwnx_dini_platform_init(struct pci_dev *pci_dev, struct rwnx_plat **rwnx_plat)
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{
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struct rwnx_dini *rwnx_dini;
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u16 pci_cmd;
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int ret = 0;
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*rwnx_plat = kzalloc(sizeof(struct rwnx_plat) + sizeof(struct rwnx_dini),
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GFP_KERNEL);
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if (!*rwnx_plat)
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return -ENOMEM;
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rwnx_dini = (struct rwnx_dini *)(*rwnx_plat)->priv;
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/* Hotplug fixups */
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pci_read_config_word(pci_dev, PCI_COMMAND, &pci_cmd);
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pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
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pci_write_config_word(pci_dev, PCI_COMMAND, pci_cmd);
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pci_write_config_byte(pci_dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES >> 2);
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ret = pci_enable_device(pci_dev);
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if (ret) {
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dev_err(&(pci_dev->dev), "pci_enable_device failed\n");
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goto out_enable;
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}
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pci_set_master(pci_dev);
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ret = pci_request_regions(pci_dev, KBUILD_MODNAME);
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if (ret) {
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dev_err(&(pci_dev->dev), "pci_request_regions failed\n");
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goto out_request;
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}
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rwnx_dini->pci_bar0_vaddr = (u8 *)pci_ioremap_bar(pci_dev, 0);
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if (!rwnx_dini->pci_bar0_vaddr) {
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dev_err(&(pci_dev->dev), "pci_ioremap_bar(%d) failed\n", 0);
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ret = -ENOMEM;
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goto out_bar0;
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}
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rwnx_dini->pci_bar4_vaddr = (u8 *)pci_ioremap_bar(pci_dev, 4);
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if (!rwnx_dini->pci_bar4_vaddr) {
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dev_err(&(pci_dev->dev), "pci_ioremap_bar(%d) failed\n", 4);
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ret = -ENOMEM;
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goto out_bar4;
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}
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(*rwnx_plat)->enable = rwnx_dini_platform_enable;
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(*rwnx_plat)->disable = rwnx_dini_platform_disable;
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(*rwnx_plat)->deinit = rwnx_dini_platform_deinit;
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(*rwnx_plat)->get_address = rwnx_dini_get_address;
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(*rwnx_plat)->ack_irq = rwnx_dini_ack_irq;
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(*rwnx_plat)->get_config_reg = rwnx_dini_get_config_reg;
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#ifdef CONFIG_RWNX_SDM
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writel(0x0000FFFF, rwnx_dini->pci_bar0_vaddr + CFPGA_BAR_TOUT);
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#endif
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return 0;
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out_bar4:
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iounmap(rwnx_dini->pci_bar0_vaddr);
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out_bar0:
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pci_release_regions(pci_dev);
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out_request:
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pci_disable_device(pci_dev);
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out_enable:
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kfree(*rwnx_plat);
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return ret;
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}
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