258 lines
7.1 KiB
C
Executable File
258 lines
7.1 KiB
C
Executable File
/******************************************************************************
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*
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* Copyright(c) 2007 - 2017 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "mp_precomp.h"
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#include "../phydm_precomp.h"
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#if (RTL8822C_SUPPORT)
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void odm_config_rf_reg_8822c(struct dm_struct *dm, u32 addr, u32 data,
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enum rf_path rf_path, u32 reg_addr)
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{
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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if (addr == 0xffe)
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_MS,
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reg_addr, data, RFREG_MASK, rf_path,
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50);
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else if (addr == 0xfe)
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,
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reg_addr, data, RFREG_MASK, rf_path,
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100);
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else {
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_RF_W, reg_addr,
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data, RFREG_MASK, rf_path, 0);
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_DELAY_US,
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reg_addr, data, RFREG_MASK, rf_path,
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1);
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}
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} else {
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if (addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else if (addr == 0xfe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_us(100);
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#else
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ODM_delay_us(100);
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#endif
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} else if (addr == 0xffff) {
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ODM_delay_us(1);
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} else {
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odm_set_rf_reg(dm, rf_path, reg_addr, RFREG_MASK, data);
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/*Add 1us delay between BB/RF register setting.*/
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ODM_delay_us(1);
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}
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}
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}
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void odm_config_rf_radio_a_8822c(struct dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1000; /* RF_Content: radioa_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8822c(dm, addr, data, RF_PATH_A, addr |
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maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioA] %08X %08X\n",
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addr, data);
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}
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void odm_config_rf_radio_b_8822c(struct dm_struct *dm, u32 addr, u32 data)
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{
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u32 content = 0x1001; /* RF_Content: radiob_txt */
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u32 maskfor_phy_set = (u32)(content & 0xE000);
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odm_config_rf_reg_8822c(dm, addr, data, RF_PATH_B, addr |
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maskfor_phy_set);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_rf: [RadioB] %08X %08X\n",
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addr, data);
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}
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void phydm_agc_lower_bound_8822c(struct dm_struct *dm, u32 addr, u32 data)
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{
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u8 rxbb_gain = (u8)(data & 0x0000001f);
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u8 mp_gain = (u8)((data & 0x003f0000) >> 16);
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u8 tab = (u8)((data & 0x03c00000) >> 22);
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if (addr != R_0x1d90)
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return;
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"data = 0x%x, mp_gain = 0x%x, tab = 0x%x, rxbb_gain = 0x%x\n",
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data, mp_gain, tab, rxbb_gain);
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if (!dm->l_bnd_detect[tab] && rxbb_gain == RXBB_MAX_GAIN_8822C) {
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dm->ofdm_rxagc_l_bnd[tab] = mp_gain;
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dm->l_bnd_detect[tab] = true;
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}
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}
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void phydm_agc_store_8822c(struct dm_struct *dm, u32 addr, u32 data)
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{
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u16 rf_gain = (u16)(data & 0x000003ff);
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u8 mp_gain = (u8)((data & 0x003f0000) >> 16);
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u8 tab = (u8)((data & 0x03c00000) >> 22);
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if (addr != R_0x1d90)
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return;
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"data = 0x%x, mp_gain = 0x%x, tab = 0x%x, rxbb_gain = 0x%x\n",
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data, mp_gain, tab, rf_gain);
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dm->agc_rf_gain_ori[tab][mp_gain] = rf_gain;
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dm->agc_rf_gain[tab][mp_gain] = rf_gain;
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if (tab > dm->agc_table_cnt)
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dm->agc_table_cnt = tab;
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}
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void odm_config_bb_agc_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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phydm_agc_lower_bound_8822c(dm, addr, data);
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phydm_agc_store_8822c(dm, addr, data);
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD)
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32, addr, data,
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bitmask, (enum rf_path)0, 0);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [AGC_TAB] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_phy_reg_pg_8822c(struct dm_struct *dm, u32 band, u32 rf_path,
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u32 tx_num, u32 addr, u32 bitmask, u32 data)
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{
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if (addr == 0xfe || addr == 0xffe) {
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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} else {
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
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addr, bitmask, data);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_StoreTxPowerByRate(dm->adapter, band, rf_path, tx_num, addr,
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bitmask, data);
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#endif
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}
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PHYDM_DBG(dm, ODM_COMP_INIT,
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"===> config_bb: [PHY_REG] %08X %08X %08X\n", addr, bitmask,
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data);
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}
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void odm_config_bb_phy_8822c(struct dm_struct *dm, u32 addr, u32 bitmask,
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u32 data)
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{
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if (dm->fw_offload_ability & PHYDM_PHY_PARAM_OFFLOAD) {
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u32 delay_time = 0;
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if (addr >= 0xf9 && addr <= 0xfe) {
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if (addr == 0xfe || addr == 0xfb)
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delay_time = 50;
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else if (addr == 0xfd || addr == 0xfa)
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delay_time = 5;
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else
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delay_time = 1;
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if (addr >= 0xfc && addr <= 0xfe)
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_MS,
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addr, data, bitmask,
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(enum rf_path)0,
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delay_time);
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else
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phydm_set_reg_by_fw(dm,
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PHYDM_HALMAC_CMD_DELAY_US,
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addr, data, bitmask,
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(enum rf_path)0,
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delay_time);
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} else
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phydm_set_reg_by_fw(dm, PHYDM_HALMAC_CMD_BB_W32,
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addr, data, bitmask,
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(enum rf_path)0, 0);
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} else {
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if (addr == 0xfe)
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#ifdef CONFIG_LONG_DELAY_ISSUE
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ODM_sleep_ms(50);
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#else
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ODM_delay_ms(50);
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#endif
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else if (addr == 0xfd)
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ODM_delay_ms(5);
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else if (addr == 0xfc)
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ODM_delay_ms(1);
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else if (addr == 0xfb)
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ODM_delay_us(50);
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else if (addr == 0xfa)
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ODM_delay_us(5);
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else if (addr == 0xf9)
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ODM_delay_us(1);
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else
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odm_set_bb_reg(dm, addr, bitmask, data);
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}
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PHYDM_DBG(dm, ODM_COMP_INIT, "===> config_bb: [PHY_REG] %08X %08X\n",
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addr, data);
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}
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void odm_config_bb_txpwr_lmt_8822c_ex(struct dm_struct *dm, u8 regulation,
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u8 band, u8 bandwidth, u8 rate_section,
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u8 rf_path, u8 channel, s8 power_limit)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit_ex(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#endif
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#if 0
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PHY_SetTxPowerLimit_ex(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#endif
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}
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void odm_config_bb_txpwr_lmt_8822c(struct dm_struct *dm, u8 *regulation,
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u8 *band, u8 *bandwidth, u8 *rate_section,
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u8 *rf_path, u8 *channel, u8 *power_limit)
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{
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#if (DM_ODM_SUPPORT_TYPE & ODM_CE)
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phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
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PHY_SetTxPowerLimit(dm, regulation, band, bandwidth, rate_section,
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rf_path, channel, power_limit);
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#endif
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}
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#endif
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