205 lines
6.6 KiB
C
205 lines
6.6 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __ETNAVIV_DRM_H__
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#define __ETNAVIV_DRM_H__
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#include "drm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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struct drm_etnaviv_timespec {
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__s64 tv_sec;
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__s64 tv_nsec;
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};
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#define ETNAVIV_PARAM_GPU_MODEL 0x01
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#define ETNAVIV_PARAM_GPU_REVISION 0x02
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#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
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#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
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#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
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#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
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#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
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#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
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#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
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#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
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#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
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#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
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#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
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#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
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#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
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#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
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#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
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#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
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#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
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#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
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#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
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#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
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#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
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#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
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#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
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#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
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#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
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#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
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#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
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#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
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#define ETNA_MAX_PIPES 4
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struct drm_etnaviv_param {
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__u32 pipe;
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__u32 param;
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__u64 value;
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};
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#define ETNA_BO_CACHE_MASK 0x000f0000
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#define ETNA_BO_CACHED 0x00010000
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#define ETNA_BO_WC 0x00020000
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#define ETNA_BO_UNCACHED 0x00040000
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#define ETNA_BO_FORCE_MMU 0x00100000
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struct drm_etnaviv_gem_new {
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__u64 size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_etnaviv_gem_info {
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__u32 handle;
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__u32 pad;
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__u64 offset;
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};
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#define ETNA_PREP_READ 0x01
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#define ETNA_PREP_WRITE 0x02
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#define ETNA_PREP_NOSYNC 0x04
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struct drm_etnaviv_gem_cpu_prep {
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__u32 handle;
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__u32 op;
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struct drm_etnaviv_timespec timeout;
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};
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struct drm_etnaviv_gem_cpu_fini {
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__u32 handle;
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__u32 flags;
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};
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struct drm_etnaviv_gem_submit_reloc {
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__u32 submit_offset;
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__u32 reloc_idx;
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__u64 reloc_offset;
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__u32 flags;
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};
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#define ETNA_SUBMIT_BO_READ 0x0001
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#define ETNA_SUBMIT_BO_WRITE 0x0002
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struct drm_etnaviv_gem_submit_bo {
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__u32 flags;
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__u32 handle;
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__u64 presumed;
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};
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#define ETNA_PM_PROCESS_PRE 0x0001
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#define ETNA_PM_PROCESS_POST 0x0002
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struct drm_etnaviv_gem_submit_pmr {
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__u32 flags;
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__u8 domain;
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__u8 pad;
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__u16 signal;
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__u32 sequence;
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__u32 read_offset;
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__u32 read_idx;
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};
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#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
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#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
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#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
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#define ETNA_SUBMIT_SOFTPIN 0x0008
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#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN)
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#define ETNA_PIPE_3D 0x00
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#define ETNA_PIPE_2D 0x01
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#define ETNA_PIPE_VG 0x02
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struct drm_etnaviv_gem_submit {
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__u32 fence;
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__u32 pipe;
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__u32 exec_state;
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__u32 nr_bos;
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__u32 nr_relocs;
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__u32 stream_size;
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__u64 bos;
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__u64 relocs;
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__u64 stream;
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__u32 flags;
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__s32 fence_fd;
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__u64 pmrs;
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__u32 nr_pmrs;
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__u32 pad;
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};
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#define ETNA_WAIT_NONBLOCK 0x01
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struct drm_etnaviv_wait_fence {
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__u32 pipe;
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__u32 fence;
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__u32 flags;
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__u32 pad;
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struct drm_etnaviv_timespec timeout;
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};
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#define ETNA_USERPTR_READ 0x01
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#define ETNA_USERPTR_WRITE 0x02
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struct drm_etnaviv_gem_userptr {
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__u64 user_ptr;
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__u64 user_size;
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__u32 flags;
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__u32 handle;
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};
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struct drm_etnaviv_gem_wait {
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__u32 pipe;
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__u32 handle;
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__u32 flags;
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__u32 pad;
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struct drm_etnaviv_timespec timeout;
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};
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struct drm_etnaviv_pm_domain {
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__u32 pipe;
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__u8 iter;
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__u8 id;
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__u16 nr_signals;
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char name[64];
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};
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struct drm_etnaviv_pm_signal {
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__u32 pipe;
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__u8 domain;
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__u8 pad;
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__u16 iter;
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__u16 id;
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char name[64];
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};
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#define DRM_ETNAVIV_GET_PARAM 0x00
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#define DRM_ETNAVIV_GEM_NEW 0x02
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#define DRM_ETNAVIV_GEM_INFO 0x03
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#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
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#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
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#define DRM_ETNAVIV_GEM_SUBMIT 0x06
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#define DRM_ETNAVIV_WAIT_FENCE 0x07
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#define DRM_ETNAVIV_GEM_USERPTR 0x08
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#define DRM_ETNAVIV_GEM_WAIT 0x09
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#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
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#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
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#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
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#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
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#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
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#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
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#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
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#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
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#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
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#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
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#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
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#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
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#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
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#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
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#ifdef __cplusplus
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}
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#endif
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#endif
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