169 lines
5.4 KiB
C
169 lines
5.4 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef VIRTGPU_DRM_H
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#define VIRTGPU_DRM_H
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#include "drm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DRM_VIRTGPU_MAP 0x01
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#define DRM_VIRTGPU_EXECBUFFER 0x02
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#define DRM_VIRTGPU_GETPARAM 0x03
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#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
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#define DRM_VIRTGPU_RESOURCE_INFO 0x05
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#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
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#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
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#define DRM_VIRTGPU_WAIT 0x08
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#define DRM_VIRTGPU_GET_CAPS 0x09
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#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
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#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
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#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
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#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
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#define VIRTGPU_EXECBUF_RING_IDX 0x04
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#define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)
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struct drm_virtgpu_map {
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__u64 offset;
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__u32 handle;
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__u32 pad;
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};
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struct drm_virtgpu_execbuffer {
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__u32 flags;
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__u32 size;
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__u64 command;
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__u64 bo_handles;
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__u32 num_bo_handles;
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__s32 fence_fd;
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__u32 ring_idx;
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__u32 pad;
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};
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#define VIRTGPU_PARAM_3D_FEATURES 1
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#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
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#define VIRTGPU_PARAM_RESOURCE_BLOB 3
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#define VIRTGPU_PARAM_HOST_VISIBLE 4
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#define VIRTGPU_PARAM_CROSS_DEVICE 5
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#define VIRTGPU_PARAM_CONTEXT_INIT 6
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#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7
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struct drm_virtgpu_getparam {
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__u64 param;
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__u64 value;
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};
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struct drm_virtgpu_resource_create {
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__u32 target;
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__u32 format;
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__u32 bind;
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__u32 width;
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__u32 height;
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__u32 depth;
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__u32 array_size;
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__u32 last_level;
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__u32 nr_samples;
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__u32 flags;
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__u32 bo_handle;
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__u32 res_handle;
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__u32 size;
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__u32 stride;
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};
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struct drm_virtgpu_resource_info {
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__u32 bo_handle;
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__u32 res_handle;
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__u32 size;
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__u32 blob_mem;
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};
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struct drm_virtgpu_3d_box {
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__u32 x;
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__u32 y;
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__u32 z;
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__u32 w;
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__u32 h;
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__u32 d;
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};
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struct drm_virtgpu_3d_transfer_to_host {
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__u32 bo_handle;
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struct drm_virtgpu_3d_box box;
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__u32 level;
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__u32 offset;
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__u32 stride;
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__u32 layer_stride;
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};
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struct drm_virtgpu_3d_transfer_from_host {
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__u32 bo_handle;
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struct drm_virtgpu_3d_box box;
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__u32 level;
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__u32 offset;
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__u32 stride;
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__u32 layer_stride;
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};
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#define VIRTGPU_WAIT_NOWAIT 1
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struct drm_virtgpu_3d_wait {
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__u32 handle;
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__u32 flags;
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};
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struct drm_virtgpu_get_caps {
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__u32 cap_set_id;
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__u32 cap_set_ver;
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__u64 addr;
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__u32 size;
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__u32 pad;
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};
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struct drm_virtgpu_resource_create_blob {
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#define VIRTGPU_BLOB_MEM_GUEST 0x0001
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#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
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#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
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#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
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#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
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#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
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__u32 blob_mem;
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__u32 blob_flags;
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__u32 bo_handle;
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__u32 res_handle;
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__u64 size;
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__u32 pad;
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__u32 cmd_size;
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__u64 cmd;
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__u64 blob_id;
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};
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#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
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#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
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#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
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struct drm_virtgpu_context_set_param {
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__u64 param;
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__u64 value;
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};
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struct drm_virtgpu_context_init {
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__u32 num_params;
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__u32 pad;
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__u64 ctx_set_params;
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};
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#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
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#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
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#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
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#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
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#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
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#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)
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#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)
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#ifdef __cplusplus
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}
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#endif
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#endif
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