384 lines
9.3 KiB
C
384 lines
9.3 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef __VMWGFX_DRM_H__
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#define __VMWGFX_DRM_H__
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#include "drm.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DRM_VMW_MAX_SURFACE_FACES 6
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#define DRM_VMW_MAX_MIP_LEVELS 24
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#define DRM_VMW_GET_PARAM 0
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#define DRM_VMW_ALLOC_DMABUF 1
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#define DRM_VMW_ALLOC_BO 1
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#define DRM_VMW_UNREF_DMABUF 2
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#define DRM_VMW_HANDLE_CLOSE 2
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#define DRM_VMW_CURSOR_BYPASS 3
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#define DRM_VMW_CONTROL_STREAM 4
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#define DRM_VMW_CLAIM_STREAM 5
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#define DRM_VMW_UNREF_STREAM 6
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#define DRM_VMW_CREATE_CONTEXT 7
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#define DRM_VMW_UNREF_CONTEXT 8
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#define DRM_VMW_CREATE_SURFACE 9
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#define DRM_VMW_UNREF_SURFACE 10
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#define DRM_VMW_REF_SURFACE 11
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#define DRM_VMW_EXECBUF 12
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#define DRM_VMW_GET_3D_CAP 13
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#define DRM_VMW_FENCE_WAIT 14
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#define DRM_VMW_FENCE_SIGNALED 15
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#define DRM_VMW_FENCE_UNREF 16
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#define DRM_VMW_FENCE_EVENT 17
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#define DRM_VMW_PRESENT 18
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#define DRM_VMW_PRESENT_READBACK 19
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#define DRM_VMW_UPDATE_LAYOUT 20
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#define DRM_VMW_CREATE_SHADER 21
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#define DRM_VMW_UNREF_SHADER 22
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#define DRM_VMW_GB_SURFACE_CREATE 23
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#define DRM_VMW_GB_SURFACE_REF 24
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#define DRM_VMW_SYNCCPU 25
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#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
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#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
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#define DRM_VMW_GB_SURFACE_REF_EXT 28
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#define DRM_VMW_MSG 29
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#define DRM_VMW_MKSSTAT_RESET 30
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#define DRM_VMW_MKSSTAT_ADD 31
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#define DRM_VMW_MKSSTAT_REMOVE 32
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#define DRM_VMW_PARAM_NUM_STREAMS 0
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#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
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#define DRM_VMW_PARAM_3D 2
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#define DRM_VMW_PARAM_HW_CAPS 3
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#define DRM_VMW_PARAM_FIFO_CAPS 4
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#define DRM_VMW_PARAM_MAX_FB_SIZE 5
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#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
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#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
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#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
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#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
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#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
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#define DRM_VMW_PARAM_SCREEN_TARGET 11
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#define DRM_VMW_PARAM_DX 12
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#define DRM_VMW_PARAM_HW_CAPS2 13
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#define DRM_VMW_PARAM_SM4_1 14
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#define DRM_VMW_PARAM_SM5 15
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#define DRM_VMW_PARAM_GL43 16
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enum drm_vmw_handle_type {
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DRM_VMW_HANDLE_LEGACY = 0,
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DRM_VMW_HANDLE_PRIME = 1
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};
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struct drm_vmw_getparam_arg {
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__u64 value;
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__u32 param;
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__u32 pad64;
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};
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struct drm_vmw_context_arg {
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__s32 cid;
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__u32 pad64;
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};
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struct drm_vmw_surface_create_req {
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__u32 flags;
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__u32 format;
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__u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
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__u64 size_addr;
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__s32 shareable;
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__s32 scanout;
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};
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struct drm_vmw_surface_arg {
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__s32 sid;
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enum drm_vmw_handle_type handle_type;
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};
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struct drm_vmw_size {
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__u32 width;
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__u32 height;
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__u32 depth;
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__u32 pad64;
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};
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union drm_vmw_surface_create_arg {
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struct drm_vmw_surface_arg rep;
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struct drm_vmw_surface_create_req req;
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};
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union drm_vmw_surface_reference_arg {
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struct drm_vmw_surface_create_req rep;
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struct drm_vmw_surface_arg req;
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};
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#define DRM_VMW_EXECBUF_VERSION 2
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#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
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#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
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struct drm_vmw_execbuf_arg {
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__u64 commands;
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__u32 command_size;
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__u32 throttle_us;
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__u64 fence_rep;
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__u32 version;
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__u32 flags;
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__u32 context_handle;
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__s32 imported_fence_fd;
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};
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struct drm_vmw_fence_rep {
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__u32 handle;
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__u32 mask;
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__u32 seqno;
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__u32 passed_seqno;
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__s32 fd;
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__s32 error;
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};
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struct drm_vmw_alloc_bo_req {
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__u32 size;
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__u32 pad64;
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};
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#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
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struct drm_vmw_bo_rep {
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__u64 map_handle;
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__u32 handle;
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__u32 cur_gmr_id;
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__u32 cur_gmr_offset;
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__u32 pad64;
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};
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#define drm_vmw_dmabuf_rep drm_vmw_bo_rep
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union drm_vmw_alloc_bo_arg {
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struct drm_vmw_alloc_bo_req req;
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struct drm_vmw_bo_rep rep;
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};
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#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
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struct drm_vmw_rect {
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__s32 x;
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__s32 y;
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__u32 w;
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__u32 h;
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};
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struct drm_vmw_control_stream_arg {
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__u32 stream_id;
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__u32 enabled;
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__u32 flags;
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__u32 color_key;
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__u32 handle;
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__u32 offset;
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__s32 format;
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__u32 size;
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__u32 width;
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__u32 height;
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__u32 pitch[3];
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__u32 pad64;
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struct drm_vmw_rect src;
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struct drm_vmw_rect dst;
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};
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#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
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#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
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struct drm_vmw_cursor_bypass_arg {
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__u32 flags;
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__u32 crtc_id;
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__s32 xpos;
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__s32 ypos;
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__s32 xhot;
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__s32 yhot;
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};
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struct drm_vmw_stream_arg {
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__u32 stream_id;
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__u32 pad64;
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};
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struct drm_vmw_get_3d_cap_arg {
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__u64 buffer;
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__u32 max_size;
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__u32 pad64;
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};
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#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
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#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
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#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
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struct drm_vmw_fence_wait_arg {
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__u32 handle;
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__s32 cookie_valid;
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__u64 kernel_cookie;
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__u64 timeout_us;
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__s32 lazy;
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__s32 flags;
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__s32 wait_options;
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__s32 pad64;
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};
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struct drm_vmw_fence_signaled_arg {
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__u32 handle;
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__u32 flags;
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__s32 signaled;
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__u32 passed_seqno;
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__u32 signaled_flags;
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__u32 pad64;
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};
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struct drm_vmw_fence_arg {
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__u32 handle;
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__u32 pad64;
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};
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#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
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struct drm_vmw_event_fence {
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struct drm_event base;
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__u64 user_data;
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__u32 tv_sec;
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__u32 tv_usec;
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};
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#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
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struct drm_vmw_fence_event_arg {
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__u64 fence_rep;
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__u64 user_data;
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__u32 handle;
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__u32 flags;
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};
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struct drm_vmw_present_arg {
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__u32 fb_id;
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__u32 sid;
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__s32 dest_x;
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__s32 dest_y;
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__u64 clips_ptr;
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__u32 num_clips;
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__u32 pad64;
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};
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struct drm_vmw_present_readback_arg {
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__u32 fb_id;
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__u32 num_clips;
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__u64 clips_ptr;
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__u64 fence_rep;
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};
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struct drm_vmw_update_layout_arg {
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__u32 num_outputs;
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__u32 pad64;
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__u64 rects;
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};
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enum drm_vmw_shader_type {
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drm_vmw_shader_type_vs = 0,
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drm_vmw_shader_type_ps,
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};
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struct drm_vmw_shader_create_arg {
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enum drm_vmw_shader_type shader_type;
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__u32 size;
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__u32 buffer_handle;
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__u32 shader_handle;
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__u64 offset;
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};
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struct drm_vmw_shader_arg {
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__u32 handle;
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__u32 pad64;
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};
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enum drm_vmw_surface_flags {
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drm_vmw_surface_flag_shareable = (1 << 0),
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drm_vmw_surface_flag_scanout = (1 << 1),
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drm_vmw_surface_flag_create_buffer = (1 << 2),
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drm_vmw_surface_flag_coherent = (1 << 3),
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};
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struct drm_vmw_gb_surface_create_req {
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__u32 svga3d_flags;
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__u32 format;
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__u32 mip_levels;
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enum drm_vmw_surface_flags drm_surface_flags;
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__u32 multisample_count;
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__u32 autogen_filter;
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__u32 buffer_handle;
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__u32 array_size;
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struct drm_vmw_size base_size;
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};
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struct drm_vmw_gb_surface_create_rep {
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__u32 handle;
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__u32 backup_size;
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__u32 buffer_handle;
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__u32 buffer_size;
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__u64 buffer_map_handle;
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};
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union drm_vmw_gb_surface_create_arg {
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struct drm_vmw_gb_surface_create_rep rep;
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struct drm_vmw_gb_surface_create_req req;
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};
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struct drm_vmw_gb_surface_ref_rep {
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struct drm_vmw_gb_surface_create_req creq;
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struct drm_vmw_gb_surface_create_rep crep;
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};
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union drm_vmw_gb_surface_reference_arg {
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struct drm_vmw_gb_surface_ref_rep rep;
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struct drm_vmw_surface_arg req;
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};
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enum drm_vmw_synccpu_flags {
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drm_vmw_synccpu_read = (1 << 0),
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drm_vmw_synccpu_write = (1 << 1),
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drm_vmw_synccpu_dontblock = (1 << 2),
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drm_vmw_synccpu_allow_cs = (1 << 3)
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};
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enum drm_vmw_synccpu_op {
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drm_vmw_synccpu_grab,
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drm_vmw_synccpu_release
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};
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struct drm_vmw_synccpu_arg {
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enum drm_vmw_synccpu_op op;
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enum drm_vmw_synccpu_flags flags;
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__u32 handle;
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__u32 pad64;
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};
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enum drm_vmw_extended_context {
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drm_vmw_context_legacy,
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drm_vmw_context_dx
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};
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union drm_vmw_extended_context_arg {
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enum drm_vmw_extended_context req;
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struct drm_vmw_context_arg rep;
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};
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struct drm_vmw_handle_close_arg {
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__u32 handle;
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__u32 pad64;
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};
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#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
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enum drm_vmw_surface_version {
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drm_vmw_gb_surface_v1,
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};
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struct drm_vmw_gb_surface_create_ext_req {
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struct drm_vmw_gb_surface_create_req base;
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enum drm_vmw_surface_version version;
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__u32 svga3d_flags_upper_32_bits;
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__u32 multisample_pattern;
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__u32 quality_level;
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__u32 buffer_byte_stride;
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__u32 must_be_zero;
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};
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union drm_vmw_gb_surface_create_ext_arg {
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struct drm_vmw_gb_surface_create_rep rep;
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struct drm_vmw_gb_surface_create_ext_req req;
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};
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struct drm_vmw_gb_surface_ref_ext_rep {
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struct drm_vmw_gb_surface_create_ext_req creq;
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struct drm_vmw_gb_surface_create_rep crep;
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};
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union drm_vmw_gb_surface_reference_ext_arg {
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struct drm_vmw_gb_surface_ref_ext_rep rep;
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struct drm_vmw_surface_arg req;
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};
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struct drm_vmw_msg_arg {
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__u64 send;
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__u64 receive;
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__s32 send_only;
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__u32 receive_len;
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};
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struct drm_vmw_mksstat_add_arg {
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__u64 stat;
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__u64 info;
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__u64 strs;
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__u64 stat_len;
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__u64 info_len;
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__u64 strs_len;
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__u64 description;
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__u64 id;
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};
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struct drm_vmw_mksstat_remove_arg {
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__u64 id;
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};
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#ifdef __cplusplus
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}
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#endif
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#endif
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