88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#ifndef _UAPI_LINUX_FPGA_DFL_H
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#define _UAPI_LINUX_FPGA_DFL_H
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#define DFL_FPGA_API_VERSION 0
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#define DFL_FPGA_MAGIC 0xB6
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#define DFL_FPGA_BASE 0
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#define DFL_PORT_BASE 0x40
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#define DFL_FME_BASE 0x80
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#define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
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#define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
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#define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
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struct dfl_fpga_port_info {
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__u32 argsz;
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__u32 flags;
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__u32 num_regions;
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__u32 num_umsgs;
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};
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#define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
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struct dfl_fpga_port_region_info {
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__u32 argsz;
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__u32 flags;
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#define DFL_PORT_REGION_READ (1 << 0)
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#define DFL_PORT_REGION_WRITE (1 << 1)
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#define DFL_PORT_REGION_MMAP (1 << 2)
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__u32 index;
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#define DFL_PORT_REGION_INDEX_AFU 0
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#define DFL_PORT_REGION_INDEX_STP 1
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__u32 padding;
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__u64 size;
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__u64 offset;
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};
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#define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
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struct dfl_fpga_port_dma_map {
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__u32 argsz;
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__u32 flags;
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__u64 user_addr;
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__u64 length;
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__u64 iova;
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};
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#define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
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struct dfl_fpga_port_dma_unmap {
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__u32 argsz;
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__u32 flags;
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__u64 iova;
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};
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#define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
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struct dfl_fpga_irq_set {
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__u32 start;
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__u32 count;
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__s32 evtfds[];
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};
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#define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5, __u32)
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#define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6, struct dfl_fpga_irq_set)
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#define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7, __u32)
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#define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8, struct dfl_fpga_irq_set)
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struct dfl_fpga_fme_port_pr {
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__u32 argsz;
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__u32 flags;
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__u32 port_id;
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__u32 buffer_size;
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__u64 buffer_address;
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};
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#define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
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#define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
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#define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
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#define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3, __u32)
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#define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4, struct dfl_fpga_irq_set)
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#endif
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