86 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
			
		
		
	
	
			86 lines
		
	
	
		
			2.3 KiB
		
	
	
	
		
			C
		
	
	
	
/****************************************************************************
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 ****************************************************************************
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 ***
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 ***   This header was automatically generated from a Linux kernel header
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 ***   of the same name, to make information necessary for userspace to
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 ***   call into the kernel available to libc.  It contains only constants,
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 ***   structures, and macros generated from the original header, and thus,
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 ***   contains no copyrightable information.
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 ***
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 ***   To edit the content of this header, modify the corresponding
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 ***   source file (e.g. under external/kernel-headers/original/) then
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 ***   run bionic/libc/kernel/tools/update_all.py
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 ***
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 ***   Any manual change here will be lost the next time this script will
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 ***   be run. You've been warned!
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 ***
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 ****************************************************************************
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 ****************************************************************************/
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#ifndef __BNXT_RE_UVERBS_ABI_H__
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#define __BNXT_RE_UVERBS_ABI_H__
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#include <linux/types.h>
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#define BNXT_RE_ABI_VERSION 1
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#define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00
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#define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10
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#define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18
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enum {
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  BNXT_RE_UCNTX_CMASK_HAVE_CCTX = 0x1ULL,
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  BNXT_RE_UCNTX_CMASK_HAVE_MODE = 0x02ULL,
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};
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enum bnxt_re_wqe_mode {
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  BNXT_QPLIB_WQE_MODE_STATIC = 0x00,
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  BNXT_QPLIB_WQE_MODE_VARIABLE = 0x01,
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  BNXT_QPLIB_WQE_MODE_INVALID = 0x02,
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};
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struct bnxt_re_uctx_resp {
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  __u32 dev_id;
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  __u32 max_qp;
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  __u32 pg_size;
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  __u32 cqe_sz;
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  __u32 max_cqd;
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  __u32 rsvd;
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  __aligned_u64 comp_mask;
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  __u32 chip_id0;
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  __u32 chip_id1;
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  __u32 mode;
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  __u32 rsvd1;
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};
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struct bnxt_re_pd_resp {
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  __u32 pdid;
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  __u32 dpi;
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  __u64 dbr;
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} __attribute__((packed, aligned(4)));
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struct bnxt_re_cq_req {
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  __aligned_u64 cq_va;
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  __aligned_u64 cq_handle;
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};
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struct bnxt_re_cq_resp {
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  __u32 cqid;
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  __u32 tail;
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  __u32 phase;
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  __u32 rsvd;
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};
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struct bnxt_re_qp_req {
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  __aligned_u64 qpsva;
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  __aligned_u64 qprva;
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  __aligned_u64 qp_handle;
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};
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struct bnxt_re_qp_resp {
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  __u32 qpid;
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  __u32 rsvd;
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};
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struct bnxt_re_srq_req {
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  __aligned_u64 srqva;
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  __aligned_u64 srq_handle;
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};
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struct bnxt_re_srq_resp {
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  __u32 srqid;
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};
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enum bnxt_re_shpg_offt {
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  BNXT_RE_BEG_RESV_OFFT = 0x00,
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  BNXT_RE_AVID_OFFT = 0x10,
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  BNXT_RE_AVID_SIZE = 0x04,
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  BNXT_RE_END_RESV_OFFT = 0xFF0
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};
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#endif
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