108 lines
4.0 KiB
LLVM
108 lines
4.0 KiB
LLVM
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=CI-HSA %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=VI-HSA %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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; ALL-LABEL {{^}}test_workgroup_id_x:
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; HSA: .amd_kernel_code_t
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; HSA: .end_amd_kernel_code_t
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s2{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_y:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 1
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; HSA: compute_pgm_rsrc2_tgid_z_en = 0
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.y()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_z:
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; HSA: compute_pgm_rsrc2_user_sgpr = 6
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; HSA: compute_pgm_rsrc2_tgid_x_en = 1
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; HSA: compute_pgm_rsrc2_tgid_y_en = 0
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; HSA: compute_pgm_rsrc2_tgid_z_en = 1
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; HSA: compute_pgm_rsrc2_tg_size_en = 0
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; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
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; HSA: enable_sgpr_private_segment_buffer = 1
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; HSA: enable_sgpr_dispatch_ptr = 0
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; HSA: enable_sgpr_queue_ptr = 0
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: enable_sgpr_dispatch_id = 0
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; HSA: enable_sgpr_flat_scratch_init = 0
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; HSA: enable_sgpr_private_segment_size = 0
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; HSA: enable_sgpr_grid_workgroup_count_x = 0
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; HSA: enable_sgpr_grid_workgroup_count_y = 0
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; HSA: enable_sgpr_grid_workgroup_count_z = 0
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; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL-NOT: [[VCOPY]]
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define void @test_workgroup_id_z(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.z()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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