110 lines
4.3 KiB
LLVM
110 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -o - %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o - %s
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; SI-LABEL:{{^}}row_filter_C1_D0:
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; SI: s_endpgm
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; Function Attrs: nounwind
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define void @row_filter_C1_D0() {
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entry:
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br i1 undef, label %for.inc.1, label %do.body.preheader
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do.body.preheader: ; preds = %entry
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%0 = insertelement <4 x i32> zeroinitializer, i32 undef, i32 1
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br i1 undef, label %do.body56.1, label %do.body90
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do.body90: ; preds = %do.body56.2, %do.body56.1, %do.body.preheader
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%1 = phi <4 x i32> [ %6, %do.body56.2 ], [ %5, %do.body56.1 ], [ %0, %do.body.preheader ]
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%2 = insertelement <4 x i32> %1, i32 undef, i32 2
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%3 = insertelement <4 x i32> %2, i32 undef, i32 3
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br i1 undef, label %do.body124.1, label %do.body.1562.preheader
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do.body.1562.preheader: ; preds = %do.body124.1, %do.body90
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%storemerge = phi <4 x i32> [ %3, %do.body90 ], [ %7, %do.body124.1 ]
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%4 = insertelement <4 x i32> undef, i32 undef, i32 1
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br label %for.inc.1
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do.body56.1: ; preds = %do.body.preheader
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%5 = insertelement <4 x i32> %0, i32 undef, i32 1
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%or.cond472.1 = or i1 undef, undef
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br i1 %or.cond472.1, label %do.body56.2, label %do.body90
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do.body56.2: ; preds = %do.body56.1
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%6 = insertelement <4 x i32> %5, i32 undef, i32 1
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br label %do.body90
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do.body124.1: ; preds = %do.body90
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%7 = insertelement <4 x i32> %3, i32 undef, i32 3
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br label %do.body.1562.preheader
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for.inc.1: ; preds = %do.body.1562.preheader, %entry
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%storemerge591 = phi <4 x i32> [ zeroinitializer, %entry ], [ %storemerge, %do.body.1562.preheader ]
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%add.i495 = add <4 x i32> %storemerge591, undef
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unreachable
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}
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; SI-LABEL: {{^}}foo:
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; SI: s_endpgm
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define amdgpu_ps void @foo() #0 {
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bb:
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br i1 undef, label %bb2, label %bb1
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bb1: ; preds = %bb
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br i1 undef, label %bb4, label %bb6
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bb2: ; preds = %bb4, %bb
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%tmp = phi float [ %tmp5, %bb4 ], [ 0.000000e+00, %bb ]
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br i1 undef, label %bb9, label %bb13
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bb4: ; preds = %bb7, %bb6, %bb1
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%tmp5 = phi float [ undef, %bb1 ], [ undef, %bb6 ], [ %tmp8, %bb7 ]
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br label %bb2
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bb6: ; preds = %bb1
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br i1 undef, label %bb7, label %bb4
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bb7: ; preds = %bb6
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%tmp8 = fmul float undef, undef
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br label %bb4
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bb9: ; preds = %bb2
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%tmp10 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tmp11 = extractelement <4 x float> %tmp10, i32 1
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%tmp12 = extractelement <4 x float> %tmp10, i32 3
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br label %bb14
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bb13: ; preds = %bb2
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br i1 undef, label %bb23, label %bb24
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bb14: ; preds = %bb27, %bb24, %bb9
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%tmp15 = phi float [ %tmp12, %bb9 ], [ undef, %bb27 ], [ 0.000000e+00, %bb24 ]
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%tmp16 = phi float [ %tmp11, %bb9 ], [ undef, %bb27 ], [ %tmp25, %bb24 ]
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%tmp17 = fmul float 10.5, %tmp16
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%tmp18 = fmul float 11.5, %tmp15
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp18, float %tmp17, float %tmp17, float %tmp17)
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ret void
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bb23: ; preds = %bb13
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br i1 undef, label %bb24, label %bb26
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bb24: ; preds = %bb26, %bb23, %bb13
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%tmp25 = phi float [ %tmp, %bb13 ], [ %tmp, %bb26 ], [ 0.000000e+00, %bb23 ]
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br i1 undef, label %bb27, label %bb14
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bb26: ; preds = %bb23
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br label %bb24
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bb27: ; preds = %bb24
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br label %bb14
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}
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; Function Attrs: nounwind readnone
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declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #1
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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