55 lines
1.5 KiB
LLVM
55 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT
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; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s
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; RUN: llc -mtriple=armv8 -mcpu=cortex-a57 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT
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declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>)
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define void @test_vec64() {
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; CHECK-LABEL: test_vec64:
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call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)
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call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>)
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; CHECK-NOTSWIFT-NOT: vmov.f64 d0,
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; CHECK: vmov.i32 d0, #0
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; CHECK: bl
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; CHECK: vmov.i32 d0, #0
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; CHECK: bl
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ret void
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}
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declare arm_aapcs_vfpcc void @take_vec128(<8 x i16>)
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define void @test_vec128() {
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; CHECK-LABEL: test_vec128:
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call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
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call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
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; CHECK-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],
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; CHECK: vmov.i32 q0, #0
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; CHECK: bl
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; CHECK: vmov.i32 q0, #0
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; CHECK: bl
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ret void
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}
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declare void @take_i32(i32)
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define void @test_i32() {
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; CHECK-LABEL: test_i32:
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call arm_aapcs_vfpcc void @take_i32(i32 0)
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call arm_aapcs_vfpcc void @take_i32(i32 0)
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; CHECK-NOTSWIFT-NOT: vmov.f64 [[ZEROREG:d[0-9]+]],
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; CHECK: mov r0, #0
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; CHECK: bl
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; CHECK: mov r0, #0
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; CHECK: bl
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; It doesn't particularly matter what Swift does here, there isn't carefully
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; crafted behaviour that we might break in Cyclone.
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ret void
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}
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