54 lines
1.8 KiB
LLVM
54 lines
1.8 KiB
LLVM
; RUN: llc -march=x86 -mcpu=generic -mattr=+sse4.2 < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
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; CHECK: movl
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; CHECK: paddw
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; CHECK: movq
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; FIXME - if this test cares about scheduling, why isn't it being checked?
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; Scheduler causes produce a different instruction order
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; ATOM: movl
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; ATOM: paddw
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; ATOM: movq
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; bitcast a v4i16 to v2i32
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define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
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entry:
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%dst.addr = alloca <2 x i32>* ; <<2 x i32>**> [#uses=2]
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%src.addr = alloca <4 x i16>* ; <<4 x i16>**> [#uses=2]
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%i = alloca i32, align 4 ; <i32*> [#uses=6]
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store <2 x i32>* %dst, <2 x i32>** %dst.addr
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store <4 x i16>* %src, <4 x i16>** %src.addr
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store i32 0, i32* %i
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br label %forcond
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forcond: ; preds = %forinc, %entry
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%tmp = load i32, i32* %i ; <i32> [#uses=1]
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%cmp = icmp slt i32 %tmp, 4 ; <i1> [#uses=1]
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br i1 %cmp, label %forbody, label %afterfor
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forbody: ; preds = %forcond
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%tmp1 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp2 = load <2 x i32>*, <2 x i32>** %dst.addr ; <<2 x i32>*> [#uses=1]
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%arrayidx = getelementptr <2 x i32>, <2 x i32>* %tmp2, i32 %tmp1 ; <<2 x i32>*> [#uses=1]
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%tmp3 = load i32, i32* %i ; <i32> [#uses=1]
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%tmp4 = load <4 x i16>*, <4 x i16>** %src.addr ; <<4 x i16>*> [#uses=1]
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%arrayidx5 = getelementptr <4 x i16>, <4 x i16>* %tmp4, i32 %tmp3 ; <<4 x i16>*> [#uses=1]
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%tmp6 = load <4 x i16>, <4 x i16>* %arrayidx5 ; <<4 x i16>> [#uses=1]
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%add = add <4 x i16> %tmp6, < i16 1, i16 1, i16 1, i16 1 > ; <<4 x i16>> [#uses=1]
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%conv = bitcast <4 x i16> %add to <2 x i32> ; <<2 x i32>> [#uses=1]
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store <2 x i32> %conv, <2 x i32>* %arrayidx
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br label %forinc
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forinc: ; preds = %forbody
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%tmp7 = load i32, i32* %i ; <i32> [#uses=1]
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%inc = add i32 %tmp7, 1 ; <i32> [#uses=1]
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store i32 %inc, i32* %i
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br label %forcond
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afterfor: ; preds = %forcond
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ret void
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}
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