58 lines
1.9 KiB
LLVM
58 lines
1.9 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=athlon | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon-tbird | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon-4 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon-xp | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon-mp | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=k8 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=opteron | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon64 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon-fx | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=k8-sse3 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=opteron-sse3 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=athlon64-sse3 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=amdfam10 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=btver1 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=btver2 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
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; RUN: llc < %s -march=x86-64 -mcpu=bdver2 | FileCheck %s
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; Verify that for the X86_64 processors that are known to have poor latency
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; double precision shift instructions we do not generate 'shld' or 'shrd'
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; instructions.
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;uint64_t lshift(uint64_t a, uint64_t b, int c)
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;{
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; return (a << c) | (b >> (64-c));
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;}
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define i64 @lshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
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entry:
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; CHECK-NOT: shld
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%sh_prom = zext i32 %c to i64
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%shl = shl i64 %a, %sh_prom
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%sub = sub nsw i32 64, %c
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%sh_prom1 = zext i32 %sub to i64
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%shr = lshr i64 %b, %sh_prom1
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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;uint64_t rshift(uint64_t a, uint64_t b, int c)
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;{
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; return (a >> c) | (b << (64-c));
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;}
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define i64 @rshift(i64 %a, i64 %b, i32 %c) nounwind readnone {
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entry:
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; CHECK-NOT: shrd
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%sh_prom = zext i32 %c to i64
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%shr = lshr i64 %a, %sh_prom
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%sub = sub nsw i32 64, %c
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%sh_prom1 = zext i32 %sub to i64
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%shl = shl i64 %b, %sh_prom1
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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