283 lines
9.1 KiB
ArmAsm
283 lines
9.1 KiB
ArmAsm
// RUN: not llvm-mc -triple=thumbv8m.base -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-BASELINE --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=UNDEF-BASELINE --check-prefix=UNDEF < %t %s
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// RUN: not llvm-mc -triple=thumbv8m.main -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-MAINLINE --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=UNDEF-MAINLINE --check-prefix=UNDEF < %t %s
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// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+dsp,+t2xtpk -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK-MAINLINE_DSP --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=UNDEF-MAINLINE_DSP --check-prefix=UNDEF < %t %s
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// Simple check that baseline is v6M and mainline is v7M
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// UNDEF-BASELINE: error: instruction requires: thumb2
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// UNDEF-MAINLINE-NOT: error: instruction requires:
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// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
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mov.w r0, r0
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// Check that .arm is invalid
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// UNDEF: target does not support ARM mode
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.arm
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// And only +dsp,+t2xtpk has DSP and t2xtpk instructions
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// UNDEF-BASELINE: error: instruction requires: arm-mode
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// UNDEF-MAINLINE: error: instruction requires: arm-mode
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// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
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qadd16 r0, r0, r0
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// UNDEF-BASELINE: error: instruction requires: arm-mode
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// UNDEF-MAINLINE: error: instruction requires: arm-mode
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// UNDEF-MAINLINE_DSP-NOT: error: instruction requires:
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uxtab16 r0, r1, r2
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// Instruction availibility checks
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// 'Barrier instructions'
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// CHECK: isb sy @ encoding: [0xbf,0xf3,0x6f,0x8f]
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isb sy
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// 'Code optimization'
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// CHECK: cbz r3, .Ltmp0 @ encoding: [0x03'A',0xb1'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
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cbz r3, 1f
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// CHECK: cbnz r3, .Ltmp0 @ encoding: [0x03'A',0xb9'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
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cbnz r3, 1f
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// CHECK: b.w .Ltmp0 @ encoding: [A,0xf0'A',A,0x90'A']
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// CHECK-NEXT: @ fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch
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b.w 1f
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// CHECK: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
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sdiv r1, r2, r3
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// CHECK: udiv r1, r2, r3 @ encoding: [0xb2,0xfb,0xf3,0xf1]
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udiv r1, r2, r3
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// 'Exclusives from ARMv7-M'
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// CHECK: clrex @ encoding: [0xbf,0xf3,0x2f,0x8f]
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clrex
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// CHECK: ldrex r1, [r2, #4] @ encoding: [0x52,0xe8,0x01,0x1f]
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ldrex r1, [r2, #4]
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// CHECK: ldrexb r1, [r2] @ encoding: [0xd2,0xe8,0x4f,0x1f]
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ldrexb r1, [r2]
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// CHECK: ldrexh r1, [r2] @ encoding: [0xd2,0xe8,0x5f,0x1f]
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ldrexh r1, [r2]
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// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
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// UNDEF-MAINLINE: error: instruction requires: !armv*m
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ldrexd r0, r1, [r2]
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// CHECK: strex r1, r2, [r3, #4] @ encoding: [0x43,0xe8,0x01,0x21]
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strex r1, r2, [r3, #4]
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// CHECK: strexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0x41,0x2f]
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strexb r1, r2, [r3]
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// CHECK: strexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0x51,0x2f]
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strexh r1, r2, [r3]
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// UNDEF-BASELINE: error: instruction requires: !armv*m thumb2
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// UNDEF-MAINLINE: error: instruction requires: !armv*m
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strexd r0, r1, r2, [r3]
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// 'XO generation'
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// CHECK: movw r1, #65535 @ encoding: [0x4f,0xf6,0xff,0x71]
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movw r1, #0xffff
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// CHECK: movt r1, #65535 @ encoding: [0xcf,0xf6,0xff,0x71]
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movt r1, #0xffff
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// 'Acquire/Release from ARMv8-A'
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// CHECK: lda r1, [r2] @ encoding: [0xd2,0xe8,0xaf,0x1f]
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lda r1, [r2]
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// CHECK: ldab r1, [r2] @ encoding: [0xd2,0xe8,0x8f,0x1f]
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ldab r1, [r2]
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// CHECK: ldah r1, [r2] @ encoding: [0xd2,0xe8,0x9f,0x1f]
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ldah r1, [r2]
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// CHECK: stl r1, [r3] @ encoding: [0xc3,0xe8,0xaf,0x1f]
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stl r1, [r3]
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// CHECK: stlb r1, [r3] @ encoding: [0xc3,0xe8,0x8f,0x1f]
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stlb r1, [r3]
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// CHECK: stlh r1, [r3] @ encoding: [0xc3,0xe8,0x9f,0x1f]
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stlh r1, [r3]
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// CHECK: ldaex r1, [r2] @ encoding: [0xd2,0xe8,0xef,0x1f]
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ldaex r1, [r2]
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// CHECK: ldaexb r1, [r2] @ encoding: [0xd2,0xe8,0xcf,0x1f]
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ldaexb r1, [r2]
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// CHECK: ldaexh r1, [r2] @ encoding: [0xd2,0xe8,0xdf,0x1f]
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ldaexh r1, [r2]
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// UNDEF: error: instruction requires: !armv*m
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ldaexd r0, r1, [r2]
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// CHECK: stlex r1, r2, [r3] @ encoding: [0xc3,0xe8,0xe1,0x2f]
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stlex r1, r2, [r3]
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// CHECK: stlexb r1, r2, [r3] @ encoding: [0xc3,0xe8,0xc1,0x2f]
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stlexb r1, r2, [r3]
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// CHECK: stlexh r1, r2, [r3] @ encoding: [0xc3,0xe8,0xd1,0x2f]
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stlexh r1, r2, [r3]
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// UNDEF: error: instruction requires: !armv*m
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stlexd r0, r1, r2, [r2]
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// ARMv8-M Security Extensions
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// CHECK: sg @ encoding: [0x7f,0xe9,0x7f,0xe9]
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sg
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// CHECK: bxns r0 @ encoding: [0x04,0x47]
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bxns r0
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// UNDEF-BASELINE: error: invalid operand for instruction
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// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
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// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
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// CHECK-MAINLINE: bxnseq r1 @ encoding: [0x0c,0x47]
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it eq
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bxnseq r1
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// CHECK: bxns lr @ encoding: [0x74,0x47]
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bxns lr
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// CHECK: blxns r0 @ encoding: [0x84,0x47]
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blxns r0
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// UNDEF-BASELINE: error: invalid operand for instruction
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// UNDEF-BASELINE: error: conditional execution not supported in Thumb1
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// CHECK-MAINLINE: it eq @ encoding: [0x08,0xbf]
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// CHECK-MAINLINE: blxnseq r1 @ encoding: [0x8c,0x47]
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it eq
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blxnseq r1
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// CHECK: tt r0, r1 @ encoding: [0x41,0xe8,0x00,0xf0]
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tt r0, r1
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// CHECK: tt r0, sp @ encoding: [0x4d,0xe8,0x00,0xf0]
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tt r0, sp
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// CHECK: tta r0, r1 @ encoding: [0x41,0xe8,0x80,0xf0]
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tta r0, r1
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// CHECK: ttt r0, r1 @ encoding: [0x41,0xe8,0x40,0xf0]
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ttt r0, r1
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// CHECK: ttat r0, r1 @ encoding: [0x41,0xe8,0xc0,0xf0]
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ttat r0, r1
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// 'Lazy Load/Store Multiple'
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// UNDEF-BASELINE: error: instruction requires: armv8m.main
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// CHECK-MAINLINE: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
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// CHECK-MAINLINE_DSP: vlldm r5 @ encoding: [0x35,0xec,0x00,0x0a]
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vlldm r5
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// UNDEF-BASELINE: error: instruction requires: armv8m.main
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// CHECK-MAINLINE: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
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// CHECK-MAINLINE_DSP: vlstm r10 @ encoding: [0x2a,0xec,0x00,0x0a]
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vlstm r10
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// New SYSm's
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MRS r1, MSP_NS
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// CHECK: mrs r1, msp_ns @ encoding: [0xef,0xf3,0x88,0x81]
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MSR PSP_NS, r2
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// CHECK: msr psp_ns, r2 @ encoding: [0x82,0xf3,0x89,0x88]
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MRS r3, PRIMASK_NS
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// CHECK: mrs r3, primask_ns @ encoding: [0xef,0xf3,0x90,0x83]
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MSR CONTROL_NS, r4
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// CHECK: msr control_ns, r4 @ encoding: [0x84,0xf3,0x94,0x88]
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MRS r5, SP_NS
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// CHECK: mrs r5, sp_ns @ encoding: [0xef,0xf3,0x98,0x85]
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MRS r6,MSPLIM
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// CHECK: mrs r6, msplim @ encoding: [0xef,0xf3,0x0a,0x86]
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MRS r7,PSPLIM
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// CHECK: mrs r7, psplim @ encoding: [0xef,0xf3,0x0b,0x87]
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MSR MSPLIM,r8
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// CHECK: msr msplim, r8 @ encoding: [0x88,0xf3,0x0a,0x88]
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MSR PSPLIM,r9
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// CHECK: msr psplim, r9 @ encoding: [0x89,0xf3,0x0b,0x88]
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MRS r10, MSPLIM_NS
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// CHECK-MAINLINE: mrs r10, msplim_ns @ encoding: [0xef,0xf3,0x8a,0x8a]
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// UNDEF-BASELINE: error: invalid operand for instruction
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MSR PSPLIM_NS, r11
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// CHECK-MAINLINE: msr psplim_ns, r11 @ encoding: [0x8b,0xf3,0x8b,0x88]
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// UNDEF-BASELINE: error: invalid operand for instruction
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MRS r12, BASEPRI_NS
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// CHECK-MAINLINE: mrs r12, basepri_ns @ encoding: [0xef,0xf3,0x91,0x8c]
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// UNDEF-BASELINE: error: invalid operand for instruction
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MRS r12, BASEPRI_MAX_NS
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// CHECK-MAINLINE: mrs r12, basepri_max_ns @ encoding: [0xef,0xf3,0x92,0x8c]
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// UNDEF-BASELINE: error: invalid operand for instruction
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MSR FAULTMASK_NS, r14
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// CHECK-MAINLINE: msr faultmask_ns, lr @ encoding: [0x8e,0xf3,0x93,0x88]
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// UNDEF-BASELINE: error: invalid operand for instruction
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// Invalid operand tests
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// UNDEF: error: invalid operand for instruction
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// UNDEF: sg #0
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sg #0
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// UNDEF: error: invalid operand for instruction
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// UNDEF: sg r0
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sg r0
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// UNDEF: error: invalid operand for instruction
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// UNDEF: bxns r0, r1
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bxns r0, r1
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// UNDEF: error: invalid operand for instruction
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// UNDEF: blxns r0, #0
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blxns r0, #0
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// UNDEF: error: invalid operand for instruction
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// UNDEF: blxns label
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blxns label
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt r0, r1, r2
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tt r0, r1, r2
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt r0, [r1]
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tt r0, [r1]
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt r0, r1, #4
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tt r0, r1, #4
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt r0, #4
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tt r0, #4
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// Unpredictable operands
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// UNDEF: error: invalid operand for instruction
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// UNDEF: blxns pc
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blxns pc
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt sp, r0
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tt sp, r0
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt pc, r0
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tt pc, r0
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// UNDEF: error: invalid operand for instruction
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// UNDEF: tt r0, pc
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tt r0, pc
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// UNDEF: error: invalid operand for instruction
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// UNDEF: vlldm pc
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vlldm pc
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// UNDEF: error: invalid operand for instruction
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// UNDEF: vlstm pc
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vlstm pc
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