2396 lines
66 KiB
Plaintext
2396 lines
66 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/clock/rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "rockchip,rk3588";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet1 = &gmac1;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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serial5 = &uart5;
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serial6 = &uart6;
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serial7 = &uart7;
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serial8 = &uart8;
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serial9 = &uart9;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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spi3 = &spi3;
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spi4 = &spi4;
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spi5 = &sfc;
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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gpio3 = &gpio3;
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gpio4 = &gpio4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_l0>;
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};
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core1 {
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cpu = <&cpu_l1>;
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};
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core2 {
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cpu = <&cpu_l2>;
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};
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core3 {
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cpu = <&cpu_l3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_b0>;
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};
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core1 {
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cpu = <&cpu_b1>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu_b2>;
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};
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core1 {
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cpu = <&cpu_b3>;
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};
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0>;
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enable-method = "psci";
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capacity-dmips-mhz = <530>;
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};
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cpu_l1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x100>;
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enable-method = "psci";
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capacity-dmips-mhz = <530>;
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};
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cpu_l2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x200>;
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enable-method = "psci";
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capacity-dmips-mhz = <530>;
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};
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cpu_l3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x300>;
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enable-method = "psci";
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capacity-dmips-mhz = <530>;
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};
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cpu_b0: cpu@400 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x400>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu_b1: cpu@500 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x500>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu_b2: cpu@600 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x600>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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cpu_b3: cpu@700 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x700>;
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enable-method = "psci";
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capacity-dmips-mhz = <1024>;
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};
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};
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arm_pmu: arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_LOW>;
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interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
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<&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
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};
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firmware: firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi: scmi {
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compatible = "arm,scmi-smc";
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shmem = <&scmi_shmem>;
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arm,smc-id = <0x82000010>;
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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assigned-clocks = <&scmi_clk SCMI_SPLL>;
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assigned-clock-rates = <700000000>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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};
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sdei: sdei {
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compatible = "arm,sdei-1.0";
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method = "smc";
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};
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};
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psci: psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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spll: spll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <702000000>;
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clock-output-names = "spll";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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xin32k: xin32k {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "xin32k";
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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};
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sram: sram@10f000 {
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compatible = "mmio-sram";
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reg = <0x0 0x0010f000 0x0 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0x0010f000 0x100>;
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scmi_shmem: scmi_shmem@0 {
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compatible = "arm,scmi-shmem";
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reg = <0x0 0x100>;
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};
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};
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usbdrd3_0: usbdrd3_0 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
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clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
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<&cru ACLK_USB3OTG0>;
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clock-names = "ref", "suspend", "bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usbdrd_dwc3_0: usb@fc000000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfc000000 0x0 0x400000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&power RK3588_PD_USB>;
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resets = <&cru SRST_A_USB3OTG0>;
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reset-names = "usb3-otg";
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dr_mode = "otg";
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phys = <&u2phy0_otg>;
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phy-names = "usb2-phy";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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};
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};
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usb_host0_ehci: usb@fc800000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host0_ohci: usb@fc840000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc840000 0x0 0x40000>;
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interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
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clock-names = "usbhost", "arbiter";
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phys = <&u2phy2_host>;
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phy-names = "usb2-phy";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ehci: usb@fc880000 {
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compatible = "generic-ehci";
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reg = <0x0 0xfc880000 0x0 0x40000>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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phys = <&u2phy3_host>;
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phy-names = "usb2-phy";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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usb_host1_ohci: usb@fc8c0000 {
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compatible = "generic-ohci";
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reg = <0x0 0xfc8c0000 0x0 0x40000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
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clock-names = "usbhost", "arbiter";
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phys = <&u2phy3_host>;
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phy-names = "usb2-phy";
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power-domains = <&power RK3588_PD_USB>;
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status = "disabled";
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};
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mmu600_pcie: iommu@fc900000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0xfc900000 0x0 0x200000>;
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interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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#iommu-cells = <1>;
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status = "disabled";
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};
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mmu600_php: iommu@fcb00000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0xfcb00000 0x0 0x200000>;
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interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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#iommu-cells = <1>;
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status = "disabled";
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};
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usbhost3_0: usbhost3_0 {
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compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
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clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
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<&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>;
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clock-names = "ref", "suspend", "bus", "utmi";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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status = "disabled";
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usbhost_dwc3_0: usb@fcd00000 {
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compatible = "snps,dwc3";
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reg = <0x0 0xfcd00000 0x0 0x400000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&power RK3588_PD_PHP>;
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resets = <&cru SRST_A_USB3OTG2>;
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reset-names = "usb3-host";
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dr_mode = "host";
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phy_type = "utmi_wide";
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snps,dis_enblslpm_quirk;
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snps,dis-u2-freeclk-exists-quirk;
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snps,dis-del-phy-power-chg-quirk;
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snps,dis-tx-ipgap-linecheck-quirk;
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status = "disabled";
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};
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};
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sys_grf: syscon@fd58c000 {
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compatible = "rockchip,rk3588-sys-grf", "syscon";
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reg = <0x0 0xfd58c000 0x0 0x1000>;
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};
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vo0_grf: syscon@fd5a6000 {
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compatible = "rockchip,rk3588-vo-grf", "syscon";
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reg = <0x0 0xfd5a6000 0x0 0x2000>;
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};
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vo1_grf: syscon@fd5a8000 {
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compatible = "rockchip,rk3588-vo-grf", "syscon";
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reg = <0x0 0xfd5a8000 0x0 0x100>;
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};
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usb_grf: syscon@fd5ac000 {
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compatible = "rockchip,rk3588-usb-grf", "syscon";
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reg = <0x0 0xfd5ac000 0x0 0x4000>;
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};
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php_grf: syscon@fd5b0000 {
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compatible = "rockchip,rk3588-php-grf", "syscon";
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reg = <0x0 0xfd5b0000 0x0 0x1000>;
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};
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pipe_phy0_grf: syscon@fd5bc000 {
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compatible = "rockchip,pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5bc000 0x0 0x100>;
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};
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pipe_phy2_grf: syscon@fd5c4000 {
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compatible = "rockchip,pipe-phy-grf", "syscon";
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reg = <0x0 0xfd5c4000 0x0 0x100>;
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};
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usbdpphy0_grf: syscon@fd5c8000 {
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compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
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reg = <0x0 0xfd5c8000 0x0 0x4000>;
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};
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usb2phy0_grf: syscon@fd5d0000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5d0000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy0: usb2-phy@0 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x0 0x10>;
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interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy0_otg: otg-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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usb2phy2_grf: syscon@fd5d8000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5d8000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy2: usb2-phy@8000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0x8000 0x10>;
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interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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u2phy2_host: host-port {
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#phy-cells = <0>;
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status = "disabled";
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};
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};
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};
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usb2phy3_grf: syscon@fd5dc000 {
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compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
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"simple-mfd";
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reg = <0x0 0xfd5dc000 0x0 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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u2phy3: usb2-phy@c000 {
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compatible = "rockchip,rk3588-usb2phy";
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reg = <0xc000 0x10>;
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interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
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resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
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reset-names = "phy", "apb";
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clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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status = "disabled";
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|
|
u2phy3_host: host-port {
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
hdptxphy0_grf: syscon@fd5e0000 {
|
|
compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
|
|
reg = <0x0 0xfd5e0000 0x0 0x100>;
|
|
};
|
|
|
|
ioc: syscon@fd5f0000 {
|
|
compatible = "rockchip,rk3588-ioc", "syscon";
|
|
reg = <0x0 0xfd5f0000 0x0 0x10000>;
|
|
};
|
|
|
|
syssram: sram@fd600000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x0 0xfd600000 0x0 0x100000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0xfd600000 0x100000>;
|
|
};
|
|
|
|
cru: clock-controller@fd7c0000 {
|
|
compatible = "rockchip,rk3588-cru";
|
|
rockchip,grf = <&php_grf>;
|
|
reg = <0x0 0xfd7c0000 0x0 0x5c000>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
|
|
assigned-clocks =
|
|
<&cru PLL_PPLL>, <&cru PLL_CPLL>,
|
|
<&cru PLL_NPLL>, <&cru PLL_GPLL>,
|
|
<&cru ARMCLK_L>, <&cru ARMCLK_B01>,
|
|
<&cru ACLK_CENTER_ROOT>, <&cru PCLK_CENTER_ROOT>,
|
|
<&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
|
|
<&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
|
|
<&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
|
|
<&cru HCLK_PMU_CM0_ROOT>;
|
|
assigned-clock-rates =
|
|
<100000000>, <1500000000>,
|
|
<850000000>, <1188000000>,
|
|
<816000000>, <1008000000>,
|
|
<600000000>, <200000000>,
|
|
<400000000>, <500000000>,
|
|
<800000000>, <100000000>,
|
|
<400000000>, <100000000>,
|
|
<200000000>;
|
|
};
|
|
|
|
i2c0: i2c@fd880000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfd880000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@fd890000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfd890000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac0 6>, <&dmac0 7>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@fd8b0000 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfd8b0000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm0m0_pins>;
|
|
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@fd8b0010 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfd8b0010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm1m0_pins>;
|
|
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@fd8b0020 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfd8b0020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm2m0_pins>;
|
|
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@fd8b0030 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfd8b0030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm3m0_pins>;
|
|
clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu: power-management@fd8d8000 {
|
|
compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
|
|
reg = <0x0 0xfd8d8000 0x0 0x400>;
|
|
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3588-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "okay";
|
|
|
|
/* These power domains are grouped by VD_NPU */
|
|
power-domain@RK3588_PD_NPU {
|
|
reg = <RK3588_PD_NPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_NPUTOP {
|
|
reg = <RK3588_PD_NPUTOP>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_NPU1 {
|
|
reg = <RK3588_PD_NPU1>;
|
|
};
|
|
power-domain@RK3588_PD_NPU2 {
|
|
reg = <RK3588_PD_NPU2>;
|
|
};
|
|
};
|
|
};
|
|
/* These power domains are grouped by VD_GPU */
|
|
power-domain@RK3588_PD_GPU {
|
|
reg = <RK3588_PD_GPU>;
|
|
};
|
|
/* These power domains are grouped by VD_VCODEC */
|
|
power-domain@RK3588_PD_VCODEC {
|
|
reg = <RK3588_PD_VCODEC>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_RKVDEC0 {
|
|
reg = <RK3588_PD_RKVDEC0>;
|
|
};
|
|
power-domain@RK3588_PD_RKVDEC1 {
|
|
reg = <RK3588_PD_RKVDEC1>;
|
|
};
|
|
power-domain@RK3588_PD_VENC0 {
|
|
reg = <RK3588_PD_VENC0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_VENC1 {
|
|
reg = <RK3588_PD_VENC1>;
|
|
};
|
|
};
|
|
};
|
|
/* These power domains are grouped by VD_LOGIC */
|
|
power-domain@RK3588_PD_VDPU {
|
|
reg = <RK3588_PD_VDPU>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_RGA30 {
|
|
reg = <RK3588_PD_RGA30>;
|
|
};
|
|
power-domain@RK3588_PD_av1 {
|
|
reg = <RK3588_PD_AV1>;
|
|
};
|
|
};
|
|
power-domain@RK3588_PD_VOP {
|
|
reg = <RK3588_PD_VOP>;
|
|
};
|
|
power-domain@RK3588_PD_VO0 {
|
|
reg = <RK3588_PD_VO0>;
|
|
};
|
|
power-domain@RK3588_PD_VO1 {
|
|
reg = <RK3588_PD_VO1>;
|
|
};
|
|
power-domain@RK3588_PD_VI {
|
|
reg = <RK3588_PD_VI>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_ISP1 {
|
|
reg = <RK3588_PD_ISP1>;
|
|
};
|
|
power-domain@RK3588_PD_FEC {
|
|
reg = <RK3588_PD_FEC>;
|
|
};
|
|
};
|
|
power-domain@RK3588_PD_RGA31 {
|
|
reg = <RK3588_PD_RGA31>;
|
|
};
|
|
power-domain@RK3588_PD_USB {
|
|
reg = <RK3588_PD_USB>;
|
|
};
|
|
power-domain@RK3588_PD_PHP {
|
|
reg = <RK3588_PD_PHP>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_GMAC {
|
|
reg = <RK3588_PD_GMAC>;
|
|
};
|
|
power-domain@RK3588_PD_PCIE {
|
|
reg = <RK3588_PD_PCIE>;
|
|
};
|
|
};
|
|
power-domain@RK3588_PD_NVM {
|
|
reg = <RK3588_PD_NVM>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
power-domain@RK3588_PD_NVM0 {
|
|
reg = <RK3588_PD_NVM0>;
|
|
};
|
|
};
|
|
power-domain@RK3588_PD_SDIO {
|
|
reg = <RK3588_PD_SDIO>;
|
|
};
|
|
power-domain@RK3588_PD_AUDIO {
|
|
reg = <RK3588_PD_AUDIO>;
|
|
};
|
|
power-domain@RK3588_PD_SDMMC {
|
|
reg = <RK3588_PD_SDMMC>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pvtm@fda40000 {
|
|
compatible = "rockchip,rk3588-bigcore0-pvtm";
|
|
reg = <0x0 0xfda40000 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pvtm@0 {
|
|
reg = <0>;
|
|
clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>;
|
|
clock-names = "clk", "pclk";
|
|
};
|
|
};
|
|
|
|
pvtm@fda50000 {
|
|
compatible = "rockchip,rk3588-bigcore1-pvtm";
|
|
reg = <0x0 0xfda50000 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pvtm@1 {
|
|
reg = <1>;
|
|
clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>;
|
|
clock-names = "clk", "pclk";
|
|
};
|
|
};
|
|
|
|
pvtm@fda60000 {
|
|
compatible = "rockchip,rk3588-litcore-pvtm";
|
|
reg = <0x0 0xfda60000 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pvtm@2 {
|
|
reg = <2>;
|
|
clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>;
|
|
clock-names = "clk", "pclk";
|
|
};
|
|
};
|
|
|
|
pvtm@fdaf0000 {
|
|
compatible = "rockchip,rk3588-npu-pvtm";
|
|
reg = <0x0 0xfdaf0000 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pvtm@3 {
|
|
reg = <3>;
|
|
clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>;
|
|
clock-names = "clk", "pclk";
|
|
resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>;
|
|
reset-names = "rts", "rst-p";
|
|
};
|
|
};
|
|
|
|
pvtm@fdb30000 {
|
|
compatible = "rockchip,rk3588-gpu-pvtm";
|
|
reg = <0x0 0xfdb30000 0x0 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pvtm@4 {
|
|
reg = <4>;
|
|
clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>;
|
|
clock-names = "clk", "pclk";
|
|
resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>;
|
|
reset-names = "rts", "rst-p";
|
|
};
|
|
};
|
|
|
|
npu0_mmu: iommu@fdab9000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdab9000 0x0 0x100>, <0x0 0xfdaba000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "npu0_mmu";
|
|
clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_NPUTOP>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
npu1_mmu: iommu@fdaca000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdaca000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "npu1_mmu";
|
|
clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_NPU1>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
npu2_mmu: iommu@fdada000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdada000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "npu2_mmu";
|
|
clocks = <&cru ACLK_NPU2>, <&cru HCLK_NPU2>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_NPU2>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdpu_mmu: iommu@fdb50800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdb50800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_vdpu_mmu";
|
|
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rga3_0_mmu: iommu@fdb60f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdb60f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rga3_0_mmu";
|
|
clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_RGA30>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rga3_1_mmu: iommu@fdb70f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdb70f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rga3_1_mmu";
|
|
clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_RGA31>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpegd_mmu: iommu@fdb90480 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdb90480 0x0 0x40>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_jpegd_mmu";
|
|
clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpege0_mmu: iommu@fdba0800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdba0800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_jpege0_mmu";
|
|
clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpege1_mmu: iommu@fdba4800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdba4800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_jpege1_mmu";
|
|
clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpege2_mmu: iommu@fdba8800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdba8800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_jpege2_mmu";
|
|
clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
jpege3_mmu: iommu@fdbac800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdbac800 0x0 0x40>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_jpege3_mmu";
|
|
clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@fdbb0800 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdbb0800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_iep_mmu";
|
|
clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3588_PD_VDPU>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvenc0_mmu: iommu@fdbdf000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
|
|
clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>;
|
|
clock-names = "aclk", "iface";
|
|
rockchip,disable-mmu-reset;
|
|
rockchip,enable-cmd-retry;
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3588_PD_VENC0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvenc1_mmu: iommu@fdbef000 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
|
|
clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>;
|
|
lock-names = "aclk", "iface";
|
|
rockchip,disable-mmu-reset;
|
|
rockchip,enable-cmd-retry;
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3588_PD_VENC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvdec0_mmu: iommu@fdc38700 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_rkvdec0_mmu";
|
|
locks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
|
|
clock-names = "aclk", "iface";
|
|
rockchip,disable-mmu-reset;
|
|
rockchip,enable-cmd-retry;
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3588_PD_RKVDEC0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkvdec1_mmu: iommu@fdc48700 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_rkvdec1_mmu";
|
|
clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
|
|
clock-names = "aclk", "iface";
|
|
rockchip,disable-mmu-reset;
|
|
rockchip,enable-cmd-retry;
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3588_PD_RKVDEC1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp0_mmu: iommu@fdcb7f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdcb7f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "isp0_mmu";
|
|
clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_VI>;
|
|
#iommu-cells = <0>;
|
|
rockchip,disable-mmu-reset;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp1_mmu: iommu@fdcc7f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdcc7f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "isp1_mmu";
|
|
clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_ISP1>;
|
|
#iommu-cells = <0>;
|
|
rockchip,disable-mmu-reset;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec0_mmu: iommu@fdcd0f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdcd0f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "fec0_mmu";
|
|
clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_FEC>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fec1_mmu: iommu@fdcd8f00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdcd8f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "fec1_mmu";
|
|
clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3588_PD_FEC>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop_mmu: iommu@fdd97e00 {
|
|
compatible = "rockchip,iommu-v2";
|
|
reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vop_mmu";
|
|
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
rockchip,disable-device-link-resume;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_tx2: spdif-tx@fddb0000 {
|
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
reg = <0x0 0xfddb0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac1 6>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru MCLK_SPDIF2_DP0>, <&cru HCLK_SPDIF2_DP0>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s4_8ch: i2s@fddc0000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfddc0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
|
|
clock-names = "mclk_tx", "hclk";
|
|
dmas = <&dmac2 0>;
|
|
dma-names = "tx";
|
|
resets = <&cru SRST_M_I2S4_8CH_TX>;
|
|
reset-names = "tx-m";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_tx3: spdif-tx@fdde0000 {
|
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
reg = <0x0 0xfdde0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac1 7>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s5_8ch: i2s@fddf0000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfddf0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
|
|
clock-names = "mclk_tx", "hclk";
|
|
dmas = <&dmac2 2>;
|
|
dma-names = "tx";
|
|
resets = <&cru SRST_M_I2S5_8CH_TX>;
|
|
reset-names = "tx-m";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s9_8ch: i2s@fddfc000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfddfc000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
|
|
clock-names = "mclk_rx", "hclk";
|
|
dmas = <&dmac2 23>;
|
|
dma-names = "rx";
|
|
resets = <&cru SRST_M_I2S9_8CH_RX>;
|
|
reset-names = "rx-m";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_rx0: spdif-rx@fde08000 {
|
|
compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
|
|
reg = <0x0 0xfde08000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac0 21>;
|
|
dma-names = "rx";
|
|
resets = <&cru SRST_M_SPDIFRX0>;
|
|
reset-names = "spdifrx-m";
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
edp0: edp@fdec0000 {
|
|
compatible = "rockchip,rk3588-edp";
|
|
reg = <0x0 0xfdec0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>,
|
|
<&cru CLK_EDP0_200M>;
|
|
clock-names = "dp", "pclk", "spdif";
|
|
resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>;
|
|
reset-names = "dp", "apb";
|
|
phys = <&hdptxphy0>;
|
|
phy-names = "dp";
|
|
power-domains = <&power RK3588_PD_VO1>;
|
|
rockchip,grf = <&vo1_grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2x1l1: pcie@fe180000 {
|
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x30 0x3f>;
|
|
clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
|
|
<&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
|
|
<&cru CLK_PCIE_AUX3>;
|
|
clock-names = "aclk_mst", "aclk_slv",
|
|
"aclk_dbi", "pclk", "aux";
|
|
device_type = "pci";
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
|
|
<0 0 0 2 &pcie2x1l1_intc 1>,
|
|
<0 0 0 3 &pcie2x1l1_intc 2>,
|
|
<0 0 0 4 &pcie2x1l1_intc 3>;
|
|
linux,pci-domain = <3>;
|
|
num-ib-windows = <8>;
|
|
num-ob-windows = <8>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x3000 &its 0x3000 0x1000>;
|
|
num-lanes = <1>;
|
|
phys = <&combphy2_psu PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy";
|
|
power-domains = <&power RK3588_PD_PHP>;
|
|
ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
|
|
0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
|
|
0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
|
|
0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
|
|
|
|
reg = <0xa 0x40c00000 0x0 0x400000>,
|
|
<0x0 0xfe180000 0x0 0x10000>;
|
|
reg-names = "pcie-dbi", "pcie-apb";
|
|
resets = <&cru SRST_PCIE3_POWER_UP>;
|
|
reset-names = "pipe";
|
|
status = "disabled";
|
|
|
|
pcie2x1l1_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
};
|
|
|
|
pcie2x1l2: pcie@fe190000 {
|
|
compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x40 0x4f>;
|
|
clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
|
|
<&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
|
|
<&cru CLK_PCIE_AUX4>;
|
|
clock-names = "aclk_mst", "aclk_slv",
|
|
"aclk_dbi", "pclk", "aux";
|
|
device_type = "pci";
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "sys", "pmc", "msg", "legacy", "err";
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
|
|
<0 0 0 2 &pcie2x1l2_intc 1>,
|
|
<0 0 0 3 &pcie2x1l2_intc 2>,
|
|
<0 0 0 4 &pcie2x1l2_intc 3>;
|
|
linux,pci-domain = <4>;
|
|
num-ib-windows = <8>;
|
|
num-ob-windows = <8>;
|
|
max-link-speed = <2>;
|
|
msi-map = <0x4000 &its 0x4000 0x1000>;
|
|
num-lanes = <1>;
|
|
phys = <&combphy0_ps PHY_TYPE_PCIE>;
|
|
phy-names = "pcie-phy";
|
|
power-domains = <&power RK3588_PD_PHP>;
|
|
ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
|
|
0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
|
|
0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
|
|
0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
|
|
reg = <0xa 0x41000000 0x0 0x400000>,
|
|
<0x0 0xfe190000 0x0 0x10000>;
|
|
reg-names = "pcie-dbi", "pcie-apb";
|
|
resets = <&cru SRST_PCIE4_POWER_UP>;
|
|
reset-names = "pipe";
|
|
status = "disabled";
|
|
|
|
pcie2x1l2_intc: legacy-interrupt-controller {
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
};
|
|
|
|
gmac1: ethernet@fe1c0000 {
|
|
compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
|
|
reg = <0x0 0xfe1c0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq", "eth_wake_irq";
|
|
rockchip,grf = <&sys_grf>;
|
|
rockchip,php_grf = <&php_grf>;
|
|
clocks = <&cru CLK_GMAC1>, <&cru ACLK_GMAC1>,
|
|
<&cru PCLK_GMAC1>, <&cru CLK_GMAC1_PTP_REF>;
|
|
clock-names = "stmmaceth", "aclk_mac",
|
|
"pclk_mac", "ptp_ref";
|
|
resets = <&cru SRST_A_GMAC1>;
|
|
reset-names = "stmmaceth";
|
|
|
|
snps,mixed-burst;
|
|
snps,tso;
|
|
|
|
snps,axi-config = <&gmac1_stmmac_axi_setup>;
|
|
snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
|
|
snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
|
|
status = "disabled";
|
|
|
|
mdio1: mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <0x1>;
|
|
#size-cells = <0x0>;
|
|
};
|
|
|
|
gmac1_stmmac_axi_setup: stmmac-axi-config {
|
|
snps,wr_osr_lmt = <4>;
|
|
snps,rd_osr_lmt = <8>;
|
|
snps,blen = <0 0 0 0 16 8 4>;
|
|
};
|
|
|
|
gmac1_mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <2>;
|
|
queue0 {};
|
|
queue1 {};
|
|
};
|
|
|
|
gmac1_mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <2>;
|
|
queue0 {};
|
|
queue1 {};
|
|
};
|
|
};
|
|
|
|
sata0: sata@fe210000 {
|
|
compatible = "snps,dwc-ahci";
|
|
reg = <0 0xfe210000 0 0x1000>;
|
|
clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
|
|
<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref";
|
|
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hostc";
|
|
phys = <&combphy0_ps PHY_TYPE_SATA>;
|
|
phy-names = "sata-phy";
|
|
ports-implemented = <0x1>;
|
|
power-domains = <&power RK3588_PD_PHP>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata2: sata@fe230000 {
|
|
compatible = "snps,dwc-ahci";
|
|
reg = <0 0xfe230000 0 0x1000>;
|
|
clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
|
|
<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>;
|
|
clock-names = "sata", "pmalive", "rxoob", "ref";
|
|
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hostc";
|
|
phys = <&combphy2_psu PHY_TYPE_SATA>;
|
|
phy-names = "sata-phy";
|
|
ports-implemented = <0x1>;
|
|
power-domains = <&power RK3588_PD_PHP>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sfc: spi@fe2b0000 {
|
|
compatible = "rockchip,sfc";
|
|
reg = <0x0 0xfe2b0000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
|
|
clock-names = "clk_sfc", "hclk_sfc";
|
|
assigned-clocks = <&cru SCLK_SFC>;
|
|
assigned-clock-rates = <100000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc: mmc@fe2c0000 {
|
|
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xfe2c0000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scmi_clk SCMI_CCLK_SD>, <&scmi_clk SCMI_HCLK_SD>,
|
|
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "ciu", "biu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
max-frequency = <200000000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio: mmc@fe2d0000 {
|
|
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xfe2d0000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
|
|
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
max-frequency = <200000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: mmc@fe2e0000 {
|
|
compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
|
|
reg = <0x0 0xfe2e0000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>;
|
|
assigned-clock-rates = <200000000>, <24000000>;
|
|
clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
|
|
<&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
|
|
<&cru TMCLK_EMMC>;
|
|
clock-names = "core", "bus", "axi", "block", "timer";
|
|
max-frequency = <200000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s0_8ch: i2s@fe470000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfe470000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
|
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
dmas = <&dmac0 0>, <&dmac0 1>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
|
|
reset-names = "tx-m", "rx-m";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_lrck
|
|
&i2s0_sclk
|
|
&i2s0_sdi0
|
|
&i2s0_sdi1
|
|
&i2s0_sdi2
|
|
&i2s0_sdi3
|
|
&i2s0_sdo0
|
|
&i2s0_sdo1
|
|
&i2s0_sdo2
|
|
&i2s0_sdo3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1_8ch: i2s@fe480000 {
|
|
compatible = "rockchip,rk3588-i2s-tdm";
|
|
reg = <0x0 0xfe480000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
|
|
clock-names = "mclk_tx", "mclk_rx", "hclk";
|
|
dmas = <&dmac0 2>, <&dmac0 3>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
|
|
reset-names = "tx-m", "rx-m";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1m0_lrck
|
|
&i2s1m0_sclk
|
|
&i2s1m0_sdi0
|
|
&i2s1m0_sdi1
|
|
&i2s1m0_sdi2
|
|
&i2s1m0_sdi3
|
|
&i2s1m0_sdo0
|
|
&i2s1m0_sdo1
|
|
&i2s1m0_sdo2
|
|
&i2s1m0_sdo3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s2_2ch: i2s@fe490000 {
|
|
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xfe490000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
dmas = <&dmac1 0>, <&dmac1 1>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s2m1_lrck
|
|
&i2s2m1_sclk
|
|
&i2s2m1_sdi
|
|
&i2s2m1_sdo>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s3_2ch: i2s@fe4a0000 {
|
|
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xfe4a0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
dmas = <&dmac1 2>, <&dmac1 3>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s3_lrck
|
|
&i2s3_sclk
|
|
&i2s3_sdi
|
|
&i2s3_sdo>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pdm0: pdm@fe4b0000 {
|
|
compatible = "rockchip,rk3588-pdm";
|
|
reg = <0x0 0xfe4b0000 0x0 0x1000>;
|
|
clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>;
|
|
clock-names = "pdm_clk", "pdm_hclk";
|
|
dmas = <&dmac0 4>;
|
|
dma-names = "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pdm0m0_clk
|
|
&pdm0m0_clk1
|
|
&pdm0m0_sdi0
|
|
&pdm0m0_sdi1
|
|
&pdm0m0_sdi2
|
|
&pdm0m0_sdi3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pdm1: pdm@fe4c0000 {
|
|
compatible = "rockchip,rk3588-pdm";
|
|
reg = <0x0 0xfe4c0000 0x0 0x1000>;
|
|
clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>;
|
|
clock-names = "pdm_clk", "pdm_hclk";
|
|
dmas = <&dmac1 4>;
|
|
dma-names = "rx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pdm1m0_clk
|
|
&pdm1m0_clk1
|
|
&pdm1m0_sdi0
|
|
&pdm1m0_sdi1
|
|
&pdm1m0_sdi2
|
|
&pdm1m0_sdi3>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vad: vad@fe4d0000 {
|
|
compatible = "rockchip,rk3588-vad";
|
|
reg = <0x0 0xfe4d0000 0x0 0x1000>;
|
|
reg-names = "vad";
|
|
clocks = <&cru HCLK_VAD>;
|
|
clock-names = "hclk";
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
|
|
rockchip,audio-src = <0>;
|
|
rockchip,det-channel = <0>;
|
|
rockchip,mode = <0>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_tx0: spdif-tx@fe4e0000 {
|
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
reg = <0x0 0xfe4e0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac0 5>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif0m0_tx>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdif_tx1: spdif-tx@fe4f0000 {
|
|
compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
|
|
reg = <0x0 0xfe4f0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dmac1 5>;
|
|
dma-names = "tx";
|
|
clock-names = "mclk", "hclk";
|
|
clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif1m0_tx>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
acdcdig_dsm: codec-digital@fe500000 {
|
|
compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
|
|
reg = <0x0 0xfe500000 0x0 0x1000>;
|
|
clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>;
|
|
clock-names = "dac", "pclk";
|
|
resets = <&cru SRST_DAC_ACDCDIG>;
|
|
reset-names = "reset" ;
|
|
rockchip,grf = <&sys_grf>;
|
|
rockchip,pwm-output-mode;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&auddsm_pins>;
|
|
#sound-dai-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hwlock: hwspinlock@fe5a0000 {
|
|
compatible = "rockchip,hwspinlock";
|
|
reg = <0 0xfe5a0000 0 0x100>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
gic: interrupt-controller@fe600000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
interrupt-controller;
|
|
|
|
reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
|
|
<0x0 0xfe680000 0 0x100000>; /* GICR */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
its: interrupt-controller@fe640000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
#msi-cells = <1>;
|
|
reg = <0x0 0xfe640000 0x0 0x20000>;
|
|
};
|
|
};
|
|
|
|
dmac0: dma-controller@fea10000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xfea10000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_DMAC0>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
arm,pl330-periph-burst;
|
|
};
|
|
|
|
dmac1: dma-controller@fea30000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xfea30000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_DMAC1>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
arm,pl330-periph-burst;
|
|
};
|
|
|
|
can0: can@fea50000 {
|
|
compatible = "rockchip,canfd-1.0";
|
|
reg = <0x0 0xfea50000 0x0 0x1000>;
|
|
iinterrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
|
|
reset-names = "can", "can-apb";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&can0m0_pins>;
|
|
tx-fifo-depth = <1>;
|
|
rx-fifo-depth = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@fea60000 {
|
|
compatible = "rockchip,canfd-1.0";
|
|
reg = <0x0 0xfea60000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
|
|
reset-names = "can", "can-apb";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&can1m0_pins>;
|
|
tx-fifo-depth = <1>;
|
|
rx-fifo-depth = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can2: can@fea70000 {
|
|
compatible = "rockchip,canfd-1.0";
|
|
reg = <0x0 0xfea70000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
|
|
reset-names = "can", "can-apb";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&can2m0_pins>;
|
|
tx-fifo-depth = <1>;
|
|
rx-fifo-depth = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hw_decompress: decompress@fea80000 {
|
|
compatible = "rockchip,hw-decompress";
|
|
reg = <0x0 0xfea80000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>;
|
|
clock-names = "aclk", "dclk", "pclk";
|
|
resets = <&cru SRST_D_DECOM>;
|
|
reset-names = "dresetn";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@fea90000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfea90000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@feaa0000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfeaa0000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@feab0000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfeab0000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@feac0000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfeac0000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@fead0000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfead0000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rktimer: timer@feae0000 {
|
|
compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
|
|
reg = <0x0 0xfeae0000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
|
|
clock-names = "pclk", "timer";
|
|
};
|
|
|
|
wdt: watchdog@feaf0000 {
|
|
compatible = "snps,dw-wdt";
|
|
reg = <0x0 0xfeaf0000 0x0 0x100>;
|
|
clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
|
|
clock-names = "tclk", "pclk";
|
|
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@feb00000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xfeb00000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&dmac0 14>, <&dmac0 15>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "high_speed";
|
|
pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
|
|
pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>;
|
|
num-cs = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@feb10000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xfeb10000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&dmac0 16>, <&dmac0 17>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "high_speed";
|
|
pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
|
|
pinctrl-1 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins_hs>;
|
|
num-cs = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@feb20000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xfeb20000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&dmac1 15>, <&dmac1 16>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "high_speed";
|
|
pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
|
|
pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>;
|
|
num-cs = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi3: spi@feb30000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xfeb30000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&dmac1 17>, <&dmac1 18>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "high_speed";
|
|
pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
|
|
pinctrl-1 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins_hs>;
|
|
num-cs = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@feb40000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb40000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac0 8>, <&dmac0 9>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart1m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@feb50000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb50000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac0 10>, <&dmac0 11>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@feb60000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb60000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac0 12>, <&dmac0 13>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart3m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@feb70000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb70000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac1 9>, <&dmac1 10>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart4m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@feb80000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb80000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac1 11>, <&dmac1 12>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart5m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@feb90000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeb90000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac1 13>, <&dmac1 14>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart6m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart7: serial@feba0000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfeba0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac2 7>, <&dmac2 8>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart7m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart8: serial@febb0000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfebb0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac2 9>, <&dmac2 10>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart8m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart9: serial@febc0000 {
|
|
compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xfebc0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
dmas = <&dmac2 11>, <&dmac2 12>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart9m0_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@febd0000 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebd0000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm4m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm5: pwm@febd0010 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebd0010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm5m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@febd0020 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebd0020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm6m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@febd0030 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebd0030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm7m0_pins>;
|
|
clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm8: pwm@febe0000 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebe0000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm8m0_pins>;
|
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm9: pwm@febe0010 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebe0010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm9m0_pins>;
|
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm10: pwm@febe0020 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebe0020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm10m0_pins>;
|
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm11: pwm@febe0030 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebe0030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm11m0_pins>;
|
|
clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm12: pwm@febf0000 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebf0000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm12m0_pins>;
|
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm13: pwm@febf0010 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebf0010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm13m0_pins>;
|
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm14: pwm@febf0020 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebf0020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm14m0_pins>;
|
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm15: pwm@febf0030 {
|
|
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
|
reg = <0x0 0xfebf0030 0x0 0x10>;
|
|
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm15m0_pins>;
|
|
clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
|
|
clock-names = "pwm", "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
tsadc: tsadc@fec00000 {
|
|
compatible = "rockchip,rk3588-tsadc";
|
|
reg = <0x0 0xfec00000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
assigned-clocks = <&cru CLK_TSADC>;
|
|
assigned-clock-rates = <2000000>;
|
|
resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>;
|
|
reset-names = "tsadc", "tsadc-apb";
|
|
#thermal-sensor-cells = <1>;
|
|
rockchip,hw-tshut-temp = <120000>;
|
|
rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
|
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
|
|
pinctrl-names = "gpio", "otpout";
|
|
pinctrl-0 = <&tsadc_gpio_func>;
|
|
pinctrl-1 = <&tsadc_shut_org>;
|
|
status = "disabled";
|
|
};
|
|
|
|
saradc: saradc@fec10000 {
|
|
compatible = "rockchip,rk3588-saradc";
|
|
reg = <0x0 0xfec10000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
|
|
clock-names = "saradc", "apb_pclk";
|
|
resets = <&cru SRST_P_SARADC>;
|
|
reset-names = "saradc-apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
mailbox0: mailbox@fec60000 {
|
|
compatible = "rockchip,rk3588-mailbox",
|
|
"rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xfec60000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX0>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mailbox1: mailbox@fec70000 {
|
|
compatible = "rockchip,rk3588-mailbox",
|
|
"rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xfec70000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX1>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c@fec80000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfec80000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c@fec90000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfec90000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c@feca0000 {
|
|
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
|
|
reg = <0x0 0xfeca0000 0x0 0x1000>;
|
|
clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
|
|
clock-names = "i2c", "pclk";
|
|
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c8m0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@fecb0000 {
|
|
compatible = "rockchip,rk3066-spi";
|
|
reg = <0x0 0xfecb0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
dmas = <&dmac2 13>, <&dmac2 14>;
|
|
dma-names = "tx", "rx";
|
|
pinctrl-names = "default", "high_speed";
|
|
pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
|
|
pinctrl-1 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins_hs>;
|
|
num-cs = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
otp: otp@fecc0000 {
|
|
compatible = "rockchip,rk3588-otp";
|
|
reg = <0x0 0xfecc0000 0x0 0x400>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
|
|
<&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>;
|
|
clock-names = "otpc", "apb", "arb", "phy";
|
|
resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
|
|
<&cru SRST_OTPC_ARB>;
|
|
reset-names = "otpc", "apb", "arb";
|
|
};
|
|
|
|
mailbox2: mailbox@fece0000 {
|
|
compatible = "rockchip,rk3588-mailbox",
|
|
"rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xfece0000 0x0 0x200>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX2>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmac2: dma-controller@fed10000 {
|
|
compatible = "arm,pl330", "arm,primecell";
|
|
reg = <0x0 0xfed10000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_DMAC2>;
|
|
clock-names = "apb_pclk";
|
|
#dma-cells = <1>;
|
|
arm,pl330-periph-burst;
|
|
};
|
|
|
|
hdptxphy0: phy@fed60000 {
|
|
compatible = "rockchip,rk3588-hdptx-phy";
|
|
reg = <0x0 0xfed60000 0x0 0x2000>;
|
|
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
|
|
clock-names = "ref", "apb";
|
|
resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
|
|
<&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
|
|
<&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
|
|
<&cru SRST_HDPTX0_LCPLL>;
|
|
reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
|
|
"lcpll";
|
|
rockchip,grf = <&hdptxphy0_grf>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbdp_phy0: phy@fed80000 {
|
|
compatible = "rockchip,rk3588-usbdp-phy";
|
|
reg = <0x0 0xfed80000 0x0 0x10000>;
|
|
rockchip,u2phy-grf = <&usb2phy0_grf>;
|
|
rockchip,usb-grf = <&usb_grf>;
|
|
rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
|
|
rockchip,vo-grf = <&vo0_grf>;
|
|
clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
|
|
<&cru CLK_USBDP_PHY0_IMMORTAL>,
|
|
<&cru PCLK_USBDPPHY0>;
|
|
clock-names = "refclk", "immortal", "pclk";
|
|
resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
|
|
<&cru SRST_USBDP_COMBO_PHY0_CMN>,
|
|
<&cru SRST_USBDP_COMBO_PHY0_LANE>,
|
|
<&cru SRST_USBDP_COMBO_PHY0_PCS>,
|
|
<&cru SRST_P_USBDPPHY0>;
|
|
reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
|
|
status = "disabled";
|
|
|
|
usbdp_phy0_dp: dp-port {
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbdp_phy0_u3: u3-port {
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
combphy0_ps: phy@fee00000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee00000 0x0 0x100>;
|
|
#phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>;
|
|
clock-names = "refclk", "apbclk";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;
|
|
reset-names = "combphy-apb", "combphy";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
combphy2_psu: phy@fee20000 {
|
|
compatible = "rockchip,rk3588-naneng-combphy";
|
|
reg = <0x0 0xfee20000 0x0 0x100>;
|
|
#phy-cells = <1>;
|
|
clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>;
|
|
clock-names = "refclk", "apbclk";
|
|
assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
|
|
assigned-clock-rates = <100000000>;
|
|
resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>;
|
|
reset-names = "combphy-apb", "combphy";
|
|
rockchip,pipe-grf = <&php_grf>;
|
|
rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
|
|
rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3588-pinctrl";
|
|
rockchip,grf = <&ioc>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
gpio0: gpio@fd8a0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xfd8a0000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 0 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@fec20000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xfec20000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 32 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@fec30000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xfec30000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 64 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@fec40000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xfec40000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 96 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio4: gpio@fec50000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xfec50000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pinctrl 0 128 32>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "rk3588s-pinctrl.dtsi"
|