384 lines
8.5 KiB
C
384 lines
8.5 KiB
C
/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PMIC_RK8XX_H_
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#define _PMIC_RK8XX_H_
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enum {
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REG_SECONDS = 0x00,
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REG_MINUTES,
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REG_HOURS,
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REG_DAYS,
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REG_MONTHS,
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REG_YEARS,
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REG_WEEKS,
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REG_ALARM_SECONDS,
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REG_ALARM_MINUTES,
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REG_ALARM_HOURS,
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REG_ALARM_DAYS,
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REG_ALARM_MONTHS,
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REG_ALARM_YEARS,
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REG_RTC_CTRL = 0x10,
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REG_RTC_STATUS,
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REG_RTC_INT,
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REG_RTC_COMP_LSB,
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REG_RTC_COMP_MSB,
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ID_MSB = 0x17,
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ID_LSB,
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REG_CLK32OUT = 0x20,
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REG_VB_MON,
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REG_THERMAL,
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REG_DCDC_EN,
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REG_LDO_EN,
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REG_SLEEP_SET_OFF1,
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REG_SLEEP_SET_OFF2,
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REG_DCDC_UV_STS,
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REG_DCDC_UV_ACT,
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REG_LDO_UV_STS,
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REG_LDO_UV_ACT,
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REG_DCDC_PG,
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REG_LDO_PG,
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REG_VOUT_MON_TDB,
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REG_BUCK1_CONFIG,
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REG_BUCK1_ON_VSEL,
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REG_BUCK1_SLP_VSEL,
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REG_BUCK1_DVS_VSEL,
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REG_BUCK2_CONFIG,
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REG_BUCK2_ON_VSEL,
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REG_BUCK2_SLP_VSEL,
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REG_BUCK2_DVS_VSEL,
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REG_BUCK3_CONFIG,
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REG_BUCK4_CONFIG,
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REG_BUCK4_ON_VSEL,
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REG_BUCK4_SLP_VSEL,
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REG_BOOST_CONFIG_REG,
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REG_LDO1_ON_VSEL,
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REG_LDO1_SLP_VSEL,
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REG_LDO2_ON_VSEL,
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REG_LDO2_SLP_VSEL,
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REG_LDO3_ON_VSEL,
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REG_LDO3_SLP_VSEL,
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REG_LDO4_ON_VSEL,
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REG_LDO4_SLP_VSEL,
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REG_LDO5_ON_VSEL,
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REG_LDO5_SLP_VSEL,
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REG_LDO6_ON_VSEL,
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REG_LDO6_SLP_VSEL,
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REG_LDO7_ON_VSEL,
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REG_LDO7_SLP_VSEL,
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REG_LDO8_ON_VSEL,
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REG_LDO8_SLP_VSEL,
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REG_DEVCTRL,
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REG_INT_STS1,
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REG_INT_STS_MSK1,
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REG_INT_STS2,
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REG_INT_STS_MSK2,
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REG_IO_POL,
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REG_OTP_VDD_EN,
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REG_H5V_EN,
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REG_SLEEP_SET_OFF,
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REG_BOOST_LDO9_ON_VSEL,
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REG_BOOST_LDO9_SLP_VSEL,
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REG_BOOST_CTRL,
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/* Not sure what this does */
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REG_DCDC_ILMAX = 0x90,
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REG_CHRG_COMP = 0x9a,
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REG_SUP_STS = 0xa0,
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REG_USB_CTRL,
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REG1_CHRG_CTRL,
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REG2_CHRG_CTRL,
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REG3_CHRG_CTRL,
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REG_BAT_CTRL,
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REG_BAT_HTS_TS1,
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REG_BAT_LTS_TS1,
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REG_BAT_HTS_TS2,
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REG_BAT_LTS_TS2,
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REG_TS_CTRL,
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REG_ADC_CTRL,
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REG_ON_SOURCE,
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REG_OFF_SOURCE,
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REG_GGCON,
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REG_GGSTS,
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REG_FRAME_SMP_INTERV,
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REG_AUTO_SLP_CUR_THR,
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REG3_GASCNT_CAL,
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REG2_GASCNT_CAL,
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REG1_GASCNT_CAL,
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REG0_GASCNT_CAL,
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REG3_GASCNT,
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REG2_GASCNT,
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REG1_GASCNT,
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REG0_GASCNT,
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REGH_BAT_CUR_AVG,
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REGL_BAT_CUR_AVG,
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REGH_TS1_ADC,
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REGL_TS1_ADC,
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REGH_TS2_ADC,
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REGL_TS2_ADC,
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REGH_BAT_OCV,
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REGL_BAT_OCV,
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REGH_BAT_VOL,
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REGL_BAT_VOL,
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REGH_RELAX_ENTRY_THRES,
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REGL_RELAX_ENTRY_THRES,
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REGH_RELAX_EXIT_THRES,
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REGL_RELAX_EXIT_THRES,
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REGH_RELAX_VOL1,
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REGL_RELAX_VOL1,
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REGH_RELAX_VOL2,
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REGL_RELAX_VOL2,
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REGH_BAT_CUR_R_CALC,
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REGL_BAT_CUR_R_CALC,
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REGH_BAT_VOL_R_CALC,
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REGL_BAT_VOL_R_CALC,
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REGH_CAL_OFFSET,
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REGL_CAL_OFFSET,
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REG_NON_ACT_TIMER_CNT,
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REGH_VCALIB0,
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REGL_VCALIB0,
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REGH_VCALIB1,
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REGL_VCALIB1,
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REGH_IOFFSET,
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REGL_IOFFSET,
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REG_SOC,
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REG3_REMAIN_CAP,
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REG2_REMAIN_CAP,
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REG1_REMAIN_CAP,
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REG0_REMAIN_CAP,
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REG_UPDAT_LEVE,
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REG3_NEW_FCC,
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REG2_NEW_FCC,
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REG1_NEW_FCC,
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REG0_NEW_FCC,
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REG_NON_ACT_TIMER_CNT_SAVE,
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REG_OCV_VOL_VALID,
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REG_REBOOT_CNT,
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REG_POFFSET,
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REG_MISC_MARK,
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REG_HALT_CNT,
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REGH_CALC_REST,
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REGL_CALC_REST,
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SAVE_DATA19,
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RK808_NUM_OF_REGS,
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};
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enum {
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RK817_REG_SYS_CFG3 = 0xf4,
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};
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enum {
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RK816_REG_DCDC_EN1 = 0x23,
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RK816_REG_DCDC_EN2,
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RK816_REG_DCDC_SLP_EN,
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RK816_REG_LDO_SLP_EN,
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RK816_REG_LDO_EN1 = 0x27,
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RK816_REG_LDO_EN2,
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};
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enum {
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RK805_ID = 0x8050,
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RK806_ID = 0x8060,
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RK808_ID = 0x0000,
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RK809_ID = 0x8090,
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RK816_ID = 0x8160,
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RK817_ID = 0x8170,
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RK818_ID = 0x8180,
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};
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enum {
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RK817_POWER_EN0 = 0xb1,
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RK817_POWER_EN1,
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RK817_POWER_EN2,
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RK817_POWER_EN3,
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};
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#define RK817_POWER_EN_SAVE0 0x99
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#define RK817_POWER_EN_SAVE1 0xa4
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#define RK817_ID_MSB 0xed
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#define RK817_ID_LSB 0xee
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#define RK8XX_ID_MSK 0xfff0
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#define RK817_PMIC_CHRG_TERM 0xe6
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#define RK817_PMIC_SYS_CFG1 0xf1
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#define RK817_PMIC_SYS_CFG3 0xf4
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#define RK817_GPIO_INT_CFG 0xfe
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#define RK8XX_ON_SOURCE 0xae
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#define RK8XX_OFF_SOURCE 0xaf
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#define RK817_BUCK4_CMIN 0xc6
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#define RK817_ON_SOURCE 0xf5
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#define RK817_OFF_SOURCE 0xf6
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#define RK817_NUM_OF_REGS 0xff
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#define RK8XX_DEVCTRL_REG 0x4b
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#define RK817_PWRON_KEY 0xf7
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#define RK8XX_LP_ACTION_MSK BIT(6)
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#define RK8XX_LP_OFF (0 << 6)
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#define RK8XX_LP_RESTART (1 << 6)
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#define RK8XX_LP_OFF_MSK BIT(4) | BIT(5)
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#define RK8XX_LP_TIME_6S (0 << 4)
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#define RK8XX_LP_TIME_8S (1 << 4)
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#define RK8XX_LP_TIME_10S (2 << 4)
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#define RK8XX_LP_TIME_12S (3 << 4)
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/* IRQ definitions */
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#define RK8XX_IRQ_PWRON_FALL 0
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#define RK8XX_IRQ_PWRON_RISE 1
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#define RK8XX_IRQ_PLUG_OUT 2
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#define RK8XX_IRQ_PLUG_IN 3
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#define RK8XX_IRQ_CHG_OK 4
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#define RK808_INT_STS_REG1 0x4c
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#define RK808_INT_MSK_REG1 0x4d
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#define RK808_IRQ_PLUG_OUT_MSK BIT(1)
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#define RK805_INT_STS_REG 0x4c
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#define RK805_INT_MSK_REG 0x4d
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#define RK805_IRQ_PWRON_FALL_MSK BIT(7)
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#define RK805_IRQ_PWRON_RISE_MSK BIT(0)
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#define RK806_CHIP_NAME 0x5A
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#define RK806_CHIP_VER 0x5B
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#define RK806_HW_VER 0x21
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#define HW_DUAL_PMIC 0x28
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#define HW_SINGLE_PMIC 0xe8
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#define RK806_CMD_READ 0
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#define RK806_CMD_WRITE BIT(7)
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#define RK806_CMD_CRC_EN BIT(6)
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#define RK806_CMD_CRC_DIS 0
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#define RK806_CMD_LEN_MSK 0x0f
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#define RK806_REG_H 0x00
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#define RK806_SYS_CFG1 0x5f
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#define RK806_PWRCTRL_CONFIG0 0x62
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#define RK806_PWRCTRL_CONFIG1 0x63
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#define RK806_VSEL_CTR_SEL0 0x64
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#define RK806_DVS_CTR_SEL4 0x6e
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#define RK806_SYS_CFG3 0x72
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#define RK806_PWRON_KEY 0x76
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#define RK806_INT_STS0 0x77
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#define RK806_INT_MSK0 0x78
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#define RK806_INT_STS1 0x79
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#define RK806_INT_MSK1 0x7A
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#define RK806_GPIO_INT_CONFIG 0x7B
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#define RK806_ON_SOURCE 0x74
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#define RK806_OFF_SOURCE 0x75
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#define RK806_IRQ_PWRON_FALL_MSK BIT(0)
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#define RK806_IRQ_PWRON_RISE_MSK BIT(1)
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#define RK806_DEV_OFF BIT(0)
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#define RK806_RST_MODE1 0x01
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#define RK806_RST_MODE2 0x02
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#define RK806_PWRCTRL_FUN_MSK 0x88
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#define RK806_VSEL_CTRL_MSK 0xcc
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#define RK806_VSEL_PWRCTRL1 0x11
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#define RK806_ENABLE_PWRCTRL 0x04
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#define RK806_VERSION_AB 0x01
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#define RK806_ABNORDET_EN 0x80
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#define RK806_VERSION_MSK 0x0f
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#define RK806_RESET_FUN_CLR 0x3f
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/* RK806 buck*/
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#define RK806_BUCK_ON_VSEL(n) (0x1a + n - 1)
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#define RK806_BUCK_SLP_VSEL(n) (0x24 + n - 1)
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#define RK806_BUCK_CONFIG(n) (0x10 + n - 1)
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#define RK806_BUCK_VSEL_MASK 0xff
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/* RK806 LDO */
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#define RK806_NLDO_ON_VSEL(n) (0x43 + n - 1)
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#define RK806_NLDO_SLP_VSEL(n) (0x48 + n - 1)
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#define RK806_NLDO_VSEL_MASK 0xff
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#define RK806_PLDO_ON_VSEL(n) (0x4e + n - 1)
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#define RK806_PLDO_SLP_VSEL(n) (0x54 + n - 1)
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#define RK806_PLDO_VSEL_MASK 0xff
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/* RK806 ENABLE */
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#define RK806_POWER_EN(n) (0x00 + n)
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#define RK806_NLDO_EN(n) (0x03 + n)
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#define RK806_PLDO_EN(n) (0x04 + n)
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#define RK806_BUCK_SUSPEND_EN 0x06
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#define RK806_NLDO_SUSPEND_EN 0x07
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#define RK806_PLDO_SUSPEND_EN 0x08
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#define RK806_RAMP_RATE_MASK1 0xc0
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#define RK806_RAMP_RATE_REG1(n) (0x10 + n)
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#define RK806_RAMP_RATE_REG1_8 0xeb
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#define RK806_RAMP_RATE_REG9_10 0xea
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#define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */
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#define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */
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#define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */
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#define RK806_PLDO0_2_MSK(pldo) (BIT(pldo + 5))
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#define RK806_PLDO0_2_SET(pldo) (BIT(pldo + 1) | RK806_PLDO0_2_MSK(pldo))
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#define RK806_PLDO0_2_CLR(pldo) RK806_PLDO0_2_MSK(pldo)
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#define RK816_INT_STS_REG1 0x49
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#define RK816_INT_MSK_REG1 0x4a
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#define RK816_INT_STS_REG3 0x4e
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#define RK816_INT_STS_MSK_REG3 0x4f
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#define RK816_IRQ_PWRON_RISE_MSK BIT(6)
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#define RK816_IRQ_PWRON_FALL_MSK BIT(5)
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#define RK816_IRQ_PLUG_OUT_MSK BIT(1)
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#define RK816_IRQ_CHR_OK_MSK BIT(2)
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#define RK818_INT_STS_REG1 0x4c
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#define RK818_INT_MSK_REG1 0x4d
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#define RK818_IRQ_PLUG_OUT_MSK BIT(1)
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#define RK818_IRQ_CHR_OK_MSK BIT(2)
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#define RK817_INT_STS_REG0 0xf8
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#define RK817_INT_MSK_REG0 0xf9
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#define RK817_IRQ_PWRON_FALL_MSK BIT(0)
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#define RK817_IRQ_PWRON_RISE_MSK BIT(1)
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#define RK817_IRQ_PLUG_OUT_MSK BIT(1)
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#define RK817_IRQ_PLUG_IN_MSK BIT(0)
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struct reg_data {
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u8 reg;
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u8 val;
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u8 mask;
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};
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struct rk8xx_reg_table {
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char *name;
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u8 reg_ctl;
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u8 reg_vol;
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};
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struct rk8xx_priv {
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struct virq_chip *irq_chip;
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struct spi_slave *slave;
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int variant;
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int irq;
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int lp_off_time;
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int lp_action;
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uint8_t sleep_pin;
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uint8_t rst_fun;
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int not_save_power_en;
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int sys_can_sd;
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};
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int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
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int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
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int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
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#endif
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