384 lines
13 KiB
C++
384 lines
13 KiB
C++
/*
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* Copyright (C) 2014 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "instruction_set_features_arm.h"
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#if defined(ART_TARGET_ANDROID) && defined(__arm__)
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#include <asm/hwcap.h>
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#include <sys/auxv.h>
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#endif
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#include "signal.h"
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#include <fstream>
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#include <android-base/logging.h>
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#include <android-base/stringprintf.h>
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#include <android-base/strings.h>
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#include "base/array_ref.h"
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#include <cpu_features_macros.h>
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#ifdef CPU_FEATURES_ARCH_ARM
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// This header can only be included on ARM targets,
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// as determined by cpu_features own define.
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#include <cpuinfo_arm.h>
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#endif
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#if defined(__arm__)
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extern "C" bool artCheckForArmSdivInstruction();
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extern "C" bool artCheckForArmv8AInstructions();
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#endif
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namespace art {
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using android::base::StringPrintf;
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromVariant(
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const std::string& variant, std::string* error_msg) {
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static const char* arm_variants_with_armv8a[] = {
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"cortex-a32",
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"cortex-a35",
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"cortex-a53",
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"cortex-a53.a57",
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"cortex-a53.a72",
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"cortex-a55",
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"cortex-a57",
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"cortex-a72",
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"cortex-a73",
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"cortex-a75",
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"cortex-a76",
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"exynos-m1",
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"kryo",
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"kryo385",
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"kryo785",
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};
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bool has_armv8a = FindVariantInArray(arm_variants_with_armv8a,
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arraysize(arm_variants_with_armv8a),
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variant);
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// Look for variants that have divide support.
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static const char* arm_variants_with_div[] = {
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"cortex-a7",
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"cortex-a12",
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"cortex-a15",
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"cortex-a17",
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"krait",
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};
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bool has_div = has_armv8a || FindVariantInArray(arm_variants_with_div,
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arraysize(arm_variants_with_div),
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variant);
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// Look for variants that have LPAE support.
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static const char* arm_variants_with_lpae[] = {
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"cortex-a7",
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"cortex-a12",
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"cortex-a15",
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"cortex-a17",
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"krait",
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};
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bool has_atomic_ldrd_strd = has_armv8a || FindVariantInArray(arm_variants_with_lpae,
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arraysize(arm_variants_with_lpae),
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variant);
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if (has_armv8a == false && has_div == false && has_atomic_ldrd_strd == false) {
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static const char* arm_variants_with_default_features[] = {
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"cortex-a5",
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"cortex-a8",
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"cortex-a9",
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"cortex-a9-mp",
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"default",
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"generic"
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};
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if (!FindVariantInArray(arm_variants_with_default_features,
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arraysize(arm_variants_with_default_features),
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variant)) {
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std::ostringstream os;
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os << "Unexpected CPU variant for Arm: " << variant << ".\n"
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<< "Known variants with armv8a support: "
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<< android::base::Join(ArrayRef<const char* const>(arm_variants_with_armv8a), ", ")
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<< ".\n"
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<< "Known variants with divide support: "
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<< android::base::Join(ArrayRef<const char* const>(arm_variants_with_div), ", ") << ".\n"
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<< "Known variants with LPAE support: "
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<< android::base::Join(ArrayRef<const char* const>(arm_variants_with_lpae), ", ") << ".\n"
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<< "Other known variants: "
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<< android::base::Join(ArrayRef<const char* const>(arm_variants_with_default_features),
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", ");
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*error_msg = os.str();
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return nullptr;
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} else {
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// Warn if we use the default features.
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LOG(WARNING) << "Using default instruction set features for ARM CPU variant (" << variant
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<< ") using conservative defaults";
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}
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}
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromBitmap(uint32_t bitmap) {
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bool has_div = (bitmap & kDivBitfield) != 0;
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bool has_atomic_ldrd_strd = (bitmap & kAtomicLdrdStrdBitfield) != 0;
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bool has_armv8a = (bitmap & kARMv8A) != 0;
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromCppDefines() {
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// Note: This will not work for now since we still build the 32-bit as __ARCH_ARM_7A__.
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#if defined(__ARM_ARCH_8A__)
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const bool has_armv8a = true;
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#else
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const bool has_armv8a = false;
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#endif
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#if defined (__ARM_ARCH_8A__) || defined(__ARM_ARCH_EXT_IDIV__)
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const bool has_div = true;
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#else
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const bool has_div = false;
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#endif
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#if defined (__ARM_ARCH_8A__) || defined(__ARM_FEATURE_LPAE)
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const bool has_atomic_ldrd_strd = true;
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#else
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const bool has_atomic_ldrd_strd = false;
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#endif
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromCpuInfo() {
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// Look in /proc/cpuinfo for features we need. Only use this when we can guarantee that
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// the kernel puts the appropriate feature flags in here. Sometimes it doesn't.
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bool has_atomic_ldrd_strd = false;
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bool has_div = false;
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bool has_armv8a = false;
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std::ifstream in("/proc/cpuinfo");
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if (!in.fail()) {
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while (!in.eof()) {
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std::string line;
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std::getline(in, line);
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if (!in.eof()) {
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LOG(INFO) << "cpuinfo line: " << line;
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if (line.find("Features") != std::string::npos) {
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LOG(INFO) << "found features";
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if (line.find("idivt") != std::string::npos) {
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// We always expect both ARM and Thumb divide instructions to be available or not
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// available.
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CHECK_NE(line.find("idiva"), std::string::npos);
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has_div = true;
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}
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if (line.find("lpae") != std::string::npos) {
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has_atomic_ldrd_strd = true;
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}
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}
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if (line.find("architecture") != std::string::npos
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&& line.find(": 8") != std::string::npos) {
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LOG(INFO) << "found architecture ARMv8";
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// Android is only run on A cores, so ARMv8 implies ARMv8-A.
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has_armv8a = true;
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// ARMv8 CPUs have LPAE and div support.
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has_div = true;
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has_atomic_ldrd_strd = true;
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}
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}
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}
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in.close();
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} else {
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LOG(ERROR) << "Failed to open /proc/cpuinfo";
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}
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromHwcap() {
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bool has_div = false;
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bool has_atomic_ldrd_strd = false;
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bool has_armv8a = false;
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#if defined(ART_TARGET_ANDROID) && defined(__arm__)
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uint64_t hwcaps = getauxval(AT_HWCAP);
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LOG(INFO) << "hwcaps=" << hwcaps;
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if ((hwcaps & HWCAP_IDIVT) != 0) {
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// We always expect both ARM and Thumb divide instructions to be available or not
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// available.
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CHECK_NE(hwcaps & HWCAP_IDIVA, 0U);
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has_div = true;
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}
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if ((hwcaps & HWCAP_LPAE) != 0) {
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has_atomic_ldrd_strd = true;
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}
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// TODO: Fix this once FPMISC makes it upstream.
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// For now we detect if we run on an ARMv8 CPU by looking for CRC32 and SHA1
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// (only available on ARMv8 CPUs).
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if ((hwcaps & HWCAP2_CRC32) != 0 && (hwcaps & HWCAP2_SHA1) != 0) {
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has_armv8a = true;
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}
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#endif
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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// A signal handler called by a fault for an illegal instruction. We record the fact in r0
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// and then increment the PC in the signal context to return to the next instruction. We know the
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// instruction is 4 bytes long.
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static void bad_instr_handle(int signo ATTRIBUTE_UNUSED,
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siginfo_t* si ATTRIBUTE_UNUSED,
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void* data) {
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#if defined(__arm__)
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struct ucontext *uc = (struct ucontext *)data;
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struct sigcontext *sc = &uc->uc_mcontext;
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sc->arm_r0 = 0; // Set R0 to #0 to signal error.
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sc->arm_pc += 4; // Skip offending instruction.
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#else
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UNUSED(data);
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#endif
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromAssembly() {
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// See if have a sdiv instruction. Register a signal handler and try to execute an sdiv
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// instruction. If we get a SIGILL then it's not supported.
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struct sigaction sa, osa;
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sa.sa_flags = SA_ONSTACK | SA_RESTART | SA_SIGINFO;
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sa.sa_sigaction = bad_instr_handle;
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sigemptyset(&sa.sa_mask);
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sigaction(SIGILL, &sa, &osa);
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bool has_div = false;
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bool has_armv8a = false;
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#if defined(__arm__)
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if (artCheckForArmSdivInstruction()) {
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has_div = true;
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}
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if (artCheckForArmv8AInstructions()) {
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has_armv8a = true;
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}
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#endif
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// Restore the signal handler.
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sigaction(SIGILL, &osa, nullptr);
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// Use compile time features to "detect" LPAE support.
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// TODO: write an assembly LPAE support test.
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#if defined (__ARM_ARCH_8A__) || defined(__ARM_FEATURE_LPAE)
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const bool has_atomic_ldrd_strd = true;
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#else
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const bool has_atomic_ldrd_strd = false;
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#endif
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(has_div,
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has_atomic_ldrd_strd,
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has_armv8a));
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}
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ArmFeaturesUniquePtr ArmInstructionSetFeatures::FromCpuFeatures() {
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#ifdef CPU_FEATURES_ARCH_ARM
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auto info = cpu_features::GetArmInfo();
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auto features = info.features;
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return ArmFeaturesUniquePtr(new ArmInstructionSetFeatures(features.idiva,
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features.lpae,
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info.architecture == 8));
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#else
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UNIMPLEMENTED(WARNING);
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return FromCppDefines();
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#endif
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}
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bool ArmInstructionSetFeatures::Equals(const InstructionSetFeatures* other) const {
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if (InstructionSet::kArm != other->GetInstructionSet()) {
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return false;
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}
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const ArmInstructionSetFeatures* other_as_arm = other->AsArmInstructionSetFeatures();
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return has_div_ == other_as_arm->has_div_
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&& has_atomic_ldrd_strd_ == other_as_arm->has_atomic_ldrd_strd_
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&& has_armv8a_ == other_as_arm->has_armv8a_;
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}
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bool ArmInstructionSetFeatures::HasAtLeast(const InstructionSetFeatures* other) const {
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if (InstructionSet::kArm != other->GetInstructionSet()) {
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return false;
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}
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const ArmInstructionSetFeatures* other_as_arm = other->AsArmInstructionSetFeatures();
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return (has_div_ || !other_as_arm->has_div_)
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&& (has_atomic_ldrd_strd_ || !other_as_arm->has_atomic_ldrd_strd_)
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&& (has_armv8a_ || !other_as_arm->has_armv8a_);
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}
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uint32_t ArmInstructionSetFeatures::AsBitmap() const {
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return (has_div_ ? kDivBitfield : 0)
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| (has_atomic_ldrd_strd_ ? kAtomicLdrdStrdBitfield : 0)
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| (has_armv8a_ ? kARMv8A : 0);
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}
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std::string ArmInstructionSetFeatures::GetFeatureString() const {
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std::string result;
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if (has_div_) {
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result += "div";
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} else {
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result += "-div";
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}
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if (has_atomic_ldrd_strd_) {
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result += ",atomic_ldrd_strd";
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} else {
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result += ",-atomic_ldrd_strd";
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}
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if (has_armv8a_) {
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result += ",armv8a";
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} else {
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result += ",-armv8a";
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}
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return result;
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}
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std::unique_ptr<const InstructionSetFeatures>
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ArmInstructionSetFeatures::AddFeaturesFromSplitString(
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const std::vector<std::string>& features, std::string* error_msg) const {
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bool has_atomic_ldrd_strd = has_atomic_ldrd_strd_;
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bool has_div = has_div_;
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bool has_armv8a = has_armv8a_;
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for (const std::string& feature : features) {
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DCHECK_EQ(android::base::Trim(feature), feature)
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<< "Feature name is not trimmed: '" << feature << "'";
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if (feature == "div") {
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has_div = true;
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} else if (feature == "-div") {
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has_div = false;
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} else if (feature == "atomic_ldrd_strd") {
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has_atomic_ldrd_strd = true;
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} else if (feature == "-atomic_ldrd_strd") {
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has_atomic_ldrd_strd = false;
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} else if (feature == "armv8a") {
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has_armv8a = true;
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} else if (feature == "-armv8a") {
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has_armv8a = false;
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} else {
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*error_msg = StringPrintf("Unknown instruction set feature: '%s'", feature.c_str());
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return nullptr;
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}
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}
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return std::unique_ptr<const InstructionSetFeatures>(
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new ArmInstructionSetFeatures(has_div, has_atomic_ldrd_strd, has_armv8a));
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}
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} // namespace art
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