425 lines
15 KiB
ArmAsm
425 lines
15 KiB
ArmAsm
%def fbinop(instr=""):
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/*
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* Generic 32-bit floating-point operation. Provide an "instr" line that
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* specifies an instruction that performs "s2 = s0 op s1". Because we
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* use the "softfp" ABI, this must be an instruction, not a function call.
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*
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* For: add-float, sub-float, mul-float, div-float
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*/
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/* floatop vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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mov r3, r0, lsr #8 @ r3<- CC
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and r2, r0, #255 @ r2<- BB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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GET_VREG_FLOAT_BY_ADDR s1, r3 @ s1<- vCC
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GET_VREG_FLOAT_BY_ADDR s0, r2 @ s0<- vBB
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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$instr @ s2<- op
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_FLOAT s2, r4, lr @ vAA<- s2
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GOTO_OPCODE ip @ jump to next instruction
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%def fbinop2addr(instr=""):
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/*
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* Generic 32-bit floating point "/2addr" binary operation. Provide
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* an "instr" line that specifies an instruction that performs
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* "s2 = s0 op s1".
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*
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* For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr
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*/
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/* binop/2addr vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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ubfx r4, rINST, #8, #4 @ r4<- A
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
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VREG_INDEX_TO_ADDR r4, r4 @ r4<- &vA
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GET_VREG_FLOAT_BY_ADDR s1, r3 @ s1<- vB
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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GET_VREG_FLOAT_BY_ADDR s0, r4 @ s0<- vA
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$instr @ s2<- op
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_FLOAT_BY_ADDR s2, r4 @ vAA<- s2 No need to clear as it's 2addr
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GOTO_OPCODE ip @ jump to next instruction
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%def fbinopWide(instr=""):
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/*
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* Generic 64-bit double-precision floating point binary operation.
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* Provide an "instr" line that specifies an instruction that performs
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* "d2 = d0 op d1".
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*
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* for: add-double, sub-double, mul-double, div-double
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*/
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/* doubleop vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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mov r3, r0, lsr #8 @ r3<- CC
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and r2, r0, #255 @ r2<- BB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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GET_VREG_DOUBLE_BY_ADDR d1, r3 @ d1<- vCC
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GET_VREG_DOUBLE_BY_ADDR d0, r2 @ d0<- vBB
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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$instr @ d2<- op
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CLEAR_SHADOW_PAIR r4, ip, lr @ Zero shadow regs
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GET_INST_OPCODE ip @ extract opcode from rINST
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VREG_INDEX_TO_ADDR r4, r4 @ r4<- &vAA
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SET_VREG_DOUBLE_BY_ADDR d2, r4 @ vAA<- d2
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GOTO_OPCODE ip @ jump to next instruction
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%def fbinopWide2addr(instr=""):
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/*
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* Generic 64-bit floating point "/2addr" binary operation. Provide
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* an "instr" line that specifies an instruction that performs
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* "d2 = d0 op d1".
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*
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* For: add-double/2addr, sub-double/2addr, mul-double/2addr,
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* div-double/2addr
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*/
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/* binop/2addr vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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ubfx r4, rINST, #8, #4 @ r4<- A
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
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CLEAR_SHADOW_PAIR r4, ip, r0 @ Zero out shadow regs
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GET_VREG_DOUBLE_BY_ADDR d1, r3 @ d1<- vB
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VREG_INDEX_TO_ADDR r4, r4 @ r4<- &vA
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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GET_VREG_DOUBLE_BY_ADDR d0, r4 @ d0<- vA
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$instr @ d2<- op
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_DOUBLE_BY_ADDR d2, r4 @ vAA<- d2
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GOTO_OPCODE ip @ jump to next instruction
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%def funop(instr=""):
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/*
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* Generic 32-bit unary floating-point operation. Provide an "instr"
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* line that specifies an instruction that performs "s1 = op s0".
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*
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* for: int-to-float, float-to-int
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*/
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/* unop vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
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GET_VREG_FLOAT_BY_ADDR s0, r3 @ s0<- vB
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ubfx r4, rINST, #8, #4 @ r4<- A
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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$instr @ s1<- op
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_FLOAT s1, r4, lr @ vA<- s1
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GOTO_OPCODE ip @ jump to next instruction
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%def funopNarrower(instr=""):
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/*
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* Generic 64bit-to-32bit unary floating point operation. Provide an
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* "instr" line that specifies an instruction that performs "s0 = op d0".
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*
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* For: double-to-int, double-to-float
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*/
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/* unop vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
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GET_VREG_DOUBLE_BY_ADDR d0, r3 @ d0<- vB
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ubfx r4, rINST, #8, #4 @ r4<- A
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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$instr @ s0<- op
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_FLOAT s0, r4, lr @ vA<- s0
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GOTO_OPCODE ip @ jump to next instruction
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%def funopWider(instr=""):
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/*
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* Generic 32bit-to-64bit floating point unary operation. Provide an
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* "instr" line that specifies an instruction that performs "d0 = op s0".
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*
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* For: int-to-double, float-to-double
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*/
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/* unop vA, vB */
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mov r3, rINST, lsr #12 @ r3<- B
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB
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GET_VREG_FLOAT_BY_ADDR s0, r3 @ s0<- vB
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ubfx r4, rINST, #8, #4 @ r4<- A
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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$instr @ d0<- op
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CLEAR_SHADOW_PAIR r4, ip, lr @ Zero shadow regs
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GET_INST_OPCODE ip @ extract opcode from rINST
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VREG_INDEX_TO_ADDR r4, r4 @ r4<- &vA
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SET_VREG_DOUBLE_BY_ADDR d0, r4 @ vA<- d0
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GOTO_OPCODE ip @ jump to next instruction
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%def op_add_double():
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% fbinopWide(instr="faddd d2, d0, d1")
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%def op_add_double_2addr():
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% fbinopWide2addr(instr="faddd d2, d0, d1")
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%def op_add_float():
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% fbinop(instr="fadds s2, s0, s1")
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%def op_add_float_2addr():
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% fbinop2addr(instr="fadds s2, s0, s1")
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%def op_cmpg_double():
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/*
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* Compare two floating-point values. Puts 0, 1, or -1 into the
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* destination register based on the results of the comparison.
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*
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* int compare(x, y) {
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* if (x == y) {
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* return 0;
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* } else if (x < y) {
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* return -1;
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* } else if (x > y) {
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* return 1;
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* } else {
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* return 1;
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* }
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* }
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*/
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/* op vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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and r2, r0, #255 @ r2<- BB
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mov r3, r0, lsr #8 @ r3<- CC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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GET_VREG_DOUBLE_BY_ADDR d0, r2 @ d0<- vBB
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GET_VREG_DOUBLE_BY_ADDR d1, r3 @ d1<- vCC
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vcmpe.f64 d0, d1 @ compare (vBB, vCC)
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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mvn r0, #0 @ r0<- -1 (default)
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GET_INST_OPCODE ip @ extract opcode from rINST
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fmstat
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it hi
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movhi r0, #1 @ (greater than, or unordered) r0<- 1
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moveq r0, #0 @ (equal) r0<- 0
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SET_VREG r0, r4 @ vAA<- r0
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GOTO_OPCODE ip @ jump to next instruction
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%def op_cmpg_float():
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/*
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* Compare two floating-point values. Puts 0, 1, or -1 into the
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* destination register based on the results of the comparison.
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*
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* int compare(x, y) {
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* if (x == y) {
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* return 0;
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* } else if (x < y) {
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* return -1;
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* } else if (x > y) {
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* return 1;
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* } else {
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* return 1;
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* }
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* }
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*/
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/* op vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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and r2, r0, #255 @ r2<- BB
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mov r3, r0, lsr #8 @ r3<- CC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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GET_VREG_FLOAT_BY_ADDR s0, r2 @ s0<- vBB
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GET_VREG_FLOAT_BY_ADDR s1, r3 @ s1<- vCC
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vcmpe.f32 s0, s1 @ compare (vBB, vCC)
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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mvn r0, #0 @ r0<- -1 (default)
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GET_INST_OPCODE ip @ extract opcode from rINST
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fmstat
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it hi
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movhi r0, #1 @ (greater than, or unordered) r0<- 1
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moveq r0, #0 @ (equal) r0<- 0
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SET_VREG r0, r4 @ vAA<- r0
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GOTO_OPCODE ip @ jump to next instruction
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%def op_cmpl_double():
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/*
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* Compare two floating-point values. Puts 0, 1, or -1 into the
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* destination register based on the results of the comparison.
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*
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* int compare(x, y) {
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* if (x == y) {
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* return 0;
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* } else if (x > y) {
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* return 1;
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* } else if (x < y) {
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* return -1;
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* } else {
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* return -1;
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* }
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* }
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*/
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/* op vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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and r2, r0, #255 @ r2<- BB
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mov r3, r0, lsr #8 @ r3<- CC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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GET_VREG_DOUBLE_BY_ADDR d0, r2 @ d0<- vBB
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GET_VREG_DOUBLE_BY_ADDR d1, r3 @ d1<- vCC
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vcmpe.f64 d0, d1 @ compare (vBB, vCC)
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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mvn r0, #0 @ r0<- -1 (default)
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GET_INST_OPCODE ip @ extract opcode from rINST
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fmstat @ export status flags
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it gt
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movgt r0, #1 @ (greater than) r1<- 1
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it eq
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moveq r0, #0 @ (equal) r1<- 0
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SET_VREG r0, r4 @ vAA<- r0
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GOTO_OPCODE ip @ jump to next instruction
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%def op_cmpl_float():
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/*
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* Compare two floating-point values. Puts 0, 1, or -1 into the
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* destination register based on the results of the comparison.
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*
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* int compare(x, y) {
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* if (x == y) {
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* return 0;
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* } else if (x > y) {
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* return 1;
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* } else if (x < y) {
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* return -1;
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* } else {
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* return -1;
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* }
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* }
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*/
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/* op vAA, vBB, vCC */
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FETCH r0, 1 @ r0<- CCBB
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mov r4, rINST, lsr #8 @ r4<- AA
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and r2, r0, #255 @ r2<- BB
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mov r3, r0, lsr #8 @ r3<- CC
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VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC
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GET_VREG_FLOAT_BY_ADDR s0, r2 @ s0<- vBB
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GET_VREG_FLOAT_BY_ADDR s1, r3 @ s1<- vCC
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vcmpe.f32 s0, s1 @ compare (vBB, vCC)
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FETCH_ADVANCE_INST 2 @ advance rPC, load rINST
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mvn r0, #0 @ r0<- -1 (default)
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GET_INST_OPCODE ip @ extract opcode from rINST
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fmstat @ export status flags
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it gt
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movgt r0, #1 @ (greater than) r1<- 1
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it eq
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moveq r0, #0 @ (equal) r1<- 0
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SET_VREG r0, r4 @ vAA<- r0
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GOTO_OPCODE ip @ jump to next instruction
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%def op_div_double():
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% fbinopWide(instr="fdivd d2, d0, d1")
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%def op_div_double_2addr():
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% fbinopWide2addr(instr="fdivd d2, d0, d1")
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%def op_div_float():
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% fbinop(instr="fdivs s2, s0, s1")
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%def op_div_float_2addr():
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% fbinop2addr(instr="fdivs s2, s0, s1")
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%def op_double_to_float():
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% funopNarrower(instr="vcvt.f32.f64 s0, d0")
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%def op_double_to_int():
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% funopNarrower(instr="vcvt.s32.f64 s0, d0")
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%def op_double_to_long():
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% unopWide(instr="bl nterp_d2l_doconv")
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%def op_float_to_double():
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% funopWider(instr="vcvt.f64.f32 d0, s0")
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%def op_float_to_int():
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% funop(instr="vcvt.s32.f32 s1, s0")
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%def op_float_to_long():
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% unopWider(instr="bl nterp_f2l_doconv")
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%def op_int_to_double():
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% funopWider(instr="vcvt.f64.s32 d0, s0")
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%def op_int_to_float():
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% funop(instr="vcvt.f32.s32 s1, s0")
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%def op_long_to_double():
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/*
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* Specialised 64-bit floating point operation.
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*
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* Note: The result will be returned in d2.
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*
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* For: long-to-double
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*/
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mov r3, rINST, lsr #12 @ r3<- B
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ubfx r4, rINST, #8, #4 @ r4<- A
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CLEAR_SHADOW_PAIR r4, ip, lr @ Zero shadow regs
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VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B]
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VREG_INDEX_TO_ADDR r4, r4 @ r4<- &fp[A]
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GET_VREG_DOUBLE_BY_ADDR d0, r3 @ d0<- vBB
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FETCH_ADVANCE_INST 1 @ advance rPC, load rINST
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vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh)
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vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl)
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vldr d3, constval$opcode
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vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl
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GET_INST_OPCODE ip @ extract opcode from rINST
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SET_VREG_DOUBLE_BY_ADDR d2, r4 @ vAA<- d2
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GOTO_OPCODE ip @ jump to next instruction
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/* literal pool helper */
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constval${opcode}:
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.8byte 0x41f0000000000000
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%def op_long_to_float():
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% unopNarrower(instr="bl __aeabi_l2f")
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%def op_mul_double():
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% fbinopWide(instr="fmuld d2, d0, d1")
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%def op_mul_double_2addr():
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% fbinopWide2addr(instr="fmuld d2, d0, d1")
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%def op_mul_float():
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% fbinop(instr="fmuls s2, s0, s1")
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%def op_mul_float_2addr():
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% fbinop2addr(instr="fmuls s2, s0, s1")
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%def op_neg_double():
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% unopWide(instr="add r1, r1, #0x80000000")
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%def op_neg_float():
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% unop(instr="add r0, r0, #0x80000000")
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%def op_rem_double():
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/* EABI doesn't define a double remainder function, but libm does */
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% binopWide(instr="bl fmod")
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%def op_rem_double_2addr():
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/* EABI doesn't define a double remainder function, but libm does */
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% binopWide2addr(instr="bl fmod")
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%def op_rem_float():
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/* EABI doesn't define a float remainder function, but libm does */
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% binop(instr="bl fmodf")
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%def op_rem_float_2addr():
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/* EABI doesn't define a float remainder function, but libm does */
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% binop2addr(instr="bl fmodf")
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%def op_sub_double():
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% fbinopWide(instr="fsubd d2, d0, d1")
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%def op_sub_double_2addr():
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% fbinopWide2addr(instr="fsubd d2, d0, d1")
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%def op_sub_float():
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% fbinop(instr="fsubs s2, s0, s1")
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%def op_sub_float_2addr():
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% fbinop2addr(instr="fsubs s2, s0, s1")
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