251 lines
6.9 KiB
ArmAsm
251 lines
6.9 KiB
ArmAsm
%def fpcmp(suff="d", nanval="pos"):
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/*
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* Compare two floating-point values. Puts 0, 1, or -1 into the
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* destination register based on the results of the comparison.
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*
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* int compare(x, y) {
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* if (x == y) {
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* return 0;
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* } else if (x < y) {
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* return -1;
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* } else if (x > y) {
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* return 1;
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* } else {
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* return nanval ? 1 : -1;
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* }
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* }
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*/
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/* op vAA, vBB, vCC */
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movzbl 3(rPC), %ecx # ecx<- CC
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movzbl 2(rPC), %eax # eax<- BB
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GET_VREG_XMM${suff} %xmm0, %eax
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xor %eax, %eax
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ucomis${suff} VREG_ADDRESS(%ecx), %xmm0
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jp .L${opcode}_nan_is_${nanval}
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je .L${opcode}_finish
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jb .L${opcode}_less
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.L${opcode}_nan_is_pos:
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incl %eax
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jmp .L${opcode}_finish
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.L${opcode}_nan_is_neg:
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.L${opcode}_less:
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decl %eax
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.L${opcode}_finish:
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SET_VREG %eax, rINST
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def fpcvt(instr="", load="", store="", wide="0"):
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/*
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* Generic 32-bit FP conversion operation.
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*/
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/* unop vA, vB */
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movzbl rINSTbl, %ecx # ecx <- A+
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sarl $$4, rINST # rINST <- B
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$load VREG_ADDRESS(rINST) # %st0 <- vB
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andb $$0xf, %cl # ecx <- A
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$instr
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$store VREG_ADDRESS(%ecx) # vA <- %st0
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.if $wide
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CLEAR_WIDE_REF %ecx
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.else
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CLEAR_REF %ecx
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.endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def sseBinop(instr="", suff=""):
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movzbl 2(rPC), %ecx # ecx <- BB
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movzbl 3(rPC), %eax # eax <- CC
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GET_VREG_XMM${suff} %xmm0, %ecx # %xmm0 <- 1st src
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#ifdef MTERP_USE_AVX
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v${instr}${suff} VREG_ADDRESS(%eax), %xmm0, %xmm0
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SET_VREG_XMM${suff} %xmm0, rINST # vAA <- %xmm0
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vpxor %xmm0, %xmm0, %xmm0
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vmovs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
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#else
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${instr}${suff} VREG_ADDRESS(%eax), %xmm0
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SET_VREG_XMM${suff} %xmm0, rINST # vAA <- %xmm0
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pxor %xmm0, %xmm0
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movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
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#endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def sseBinop2Addr(instr="", suff=""):
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movzx rINSTbl, %ecx # ecx <- A+
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andl $$0xf, %ecx # ecx <- A
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GET_VREG_XMM${suff} %xmm0, %ecx # %xmm0 <- 1st src
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sarl $$4, rINST # rINST<- B
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#ifdef MTERP_USE_AVX
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v${instr}${suff} VREG_ADDRESS(rINST), %xmm0, %xmm0
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SET_VREG_XMM${suff} %xmm0, %ecx # vAA<- %xmm0
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vpxor %xmm0, %xmm0, %xmm0
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vmovs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
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#else
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${instr}${suff} VREG_ADDRESS(rINST), %xmm0
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SET_VREG_XMM${suff} %xmm0, %ecx # vAA<- %xmm0
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pxor %xmm0, %xmm0
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movs${suff} %xmm0, VREG_REF_ADDRESS(rINST) # clear ref
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#endif
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_add_double():
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% sseBinop(instr="adds", suff="d")
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%def op_add_double_2addr():
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% sseBinop2Addr(instr="adds", suff="d")
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%def op_add_float():
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% sseBinop(instr="adds", suff="s")
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%def op_add_float_2addr():
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% sseBinop2Addr(instr="adds", suff="s")
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%def op_cmpg_double():
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% fpcmp(suff="d", nanval="pos")
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%def op_cmpg_float():
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% fpcmp(suff="s", nanval="pos")
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%def op_cmpl_double():
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% fpcmp(suff="d", nanval="neg")
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%def op_cmpl_float():
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% fpcmp(suff="s", nanval="neg")
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%def op_div_double():
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% sseBinop(instr="divs", suff="d")
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%def op_div_double_2addr():
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% sseBinop2Addr(instr="divs", suff="d")
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%def op_div_float():
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% sseBinop(instr="divs", suff="s")
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%def op_div_float_2addr():
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% sseBinop2Addr(instr="divs", suff="s")
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%def op_double_to_float():
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% fpcvt(load="fldl", store="fstps")
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%def op_double_to_int():
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% cvtfp_int(srcdouble="1", tgtlong="0")
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%def op_double_to_long():
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% cvtfp_int(srcdouble="1", tgtlong="1")
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%def op_float_to_double():
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% fpcvt(load="flds", store="fstpl", wide="1")
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%def op_float_to_int():
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% cvtfp_int(srcdouble="0", tgtlong="0")
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%def op_float_to_long():
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% cvtfp_int(srcdouble="0", tgtlong="1")
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%def op_int_to_double():
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% fpcvt(load="fildl", store="fstpl", wide="1")
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%def op_int_to_float():
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% fpcvt(load="fildl", store="fstps")
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%def op_long_to_double():
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% fpcvt(load="fildll", store="fstpl", wide="1")
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%def op_long_to_float():
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% fpcvt(load="fildll", store="fstps")
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%def op_mul_double():
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% sseBinop(instr="muls", suff="d")
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%def op_mul_double_2addr():
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% sseBinop2Addr(instr="muls", suff="d")
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%def op_mul_float():
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% sseBinop(instr="muls", suff="s")
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%def op_mul_float_2addr():
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% sseBinop2Addr(instr="muls", suff="s")
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%def op_neg_double():
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% fpcvt(instr="fchs", load="fldl", store="fstpl", wide="1")
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%def op_neg_float():
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% fpcvt(instr="fchs", load="flds", store="fstps")
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%def op_rem_double():
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/* rem_double vAA, vBB, vCC */
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movzbl 3(rPC), %ecx # ecx <- BB
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movzbl 2(rPC), %eax # eax <- CC
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fldl VREG_ADDRESS(%ecx) # %st1 <- fp[vBB]
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fldl VREG_ADDRESS(%eax) # %st0 <- fp[vCC]
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1:
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fprem
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fstsw %ax
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sahf
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jp 1b
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fstp %st(1)
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fstpl VREG_ADDRESS(rINST) # fp[vAA] <- %st
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CLEAR_WIDE_REF rINST
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def op_rem_double_2addr():
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/* rem_double/2addr vA, vB */
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movzx rINSTbl, %ecx # ecx <- A+
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sarl $$4, rINST # rINST <- B
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fldl VREG_ADDRESS(rINST) # vB to fp stack
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andb $$0xf, %cl # ecx <- A
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fldl VREG_ADDRESS(%ecx) # vA to fp stack
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1:
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fprem
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fstsw %ax
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sahf
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jp 1b
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fstp %st(1)
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fstpl VREG_ADDRESS(%ecx) # %st to vA
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CLEAR_WIDE_REF %ecx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_rem_float():
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/* rem_float vAA, vBB, vCC */
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movzbl 3(rPC), %ecx # ecx <- BB
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movzbl 2(rPC), %eax # eax <- CC
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flds VREG_ADDRESS(%ecx) # vBB to fp stack
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flds VREG_ADDRESS(%eax) # vCC to fp stack
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1:
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fprem
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fstsw %ax
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sahf
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jp 1b
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fstp %st(1)
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fstps VREG_ADDRESS(rINST) # %st to vAA
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CLEAR_REF rINST
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
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%def op_rem_float_2addr():
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/* rem_float/2addr vA, vB */
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movzx rINSTbl, %ecx # ecx <- A+
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sarl $$4, rINST # rINST <- B
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flds VREG_ADDRESS(rINST) # vB to fp stack
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andb $$0xf, %cl # ecx <- A
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flds VREG_ADDRESS(%ecx) # vA to fp stack
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1:
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fprem
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fstsw %ax
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sahf
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jp 1b
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fstp %st(1)
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fstps VREG_ADDRESS(%ecx) # %st to vA
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CLEAR_REF %ecx
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ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
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%def op_sub_double():
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% sseBinop(instr="subs", suff="d")
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%def op_sub_double_2addr():
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% sseBinop2Addr(instr="subs", suff="d")
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%def op_sub_float():
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% sseBinop(instr="subs", suff="s")
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%def op_sub_float_2addr():
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% sseBinop2Addr(instr="subs", suff="s")
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